FPGA: question about dynamic FIFO flush

[Pierre_F]

HELLO!

in my FPGA application, at 100kHz rate, I want to get a signal profile from my modules, made of 1024 points maximum, When a PWM = TRUE

the TRUE state of PWM last 400us (40 tops at 100khz ->40 values in the FIFO)
the FALSE state of PWM lasts 0.1sec
Data acquisition starts from a binary PWM TRUE and stops at the 1024th point OR if the binary PWM goes FALSE

the solution I used: flush and fullfil a FIFO at start of PWM TRUE, and do nothing at PWM FALSE

here is what it looks like from FPGA POV (greyed out statuses are normal: I'm screenshoting from out of the project) (measurementAllowed signal is the PWM)

and from host POV: (acquisition)

 

strangely, the flush don't seem to work, despite binary signal switches correctly and respects the PWM rate (tested)

The output "element remaining" continues to increase until 1024 and is not flushed when  PWM  switches to TRUE

questions: Do I use the FIFO in an appropriate way? and what about the flush method?

Is it acceptable to replace it by a simple 1024 elts table+"replace array  subset.vi" and pull it up as a I/O node from FPGA to host?

thanks in advance for the answers