FPGA simulation exceeds maximum simulated time

[Chris_12345]

I am running a very simple FPGA simulation (LV2014) which appears to function correctly. However, after 60 seconds of operation, I get the following pop-up:

     LabVIEW FPGA reported the following error:

     The simulation has exceeded the maximum simulated time.

Checking on-line, it looks like the maximum simulated time should be 9223372 seconds.

Any ideas on what might be causing the shortened time?

[Muri777]

Hi.

Taken from http://zone.ni.com/reference/en-XX/help/371599K-01/lvfpgahelp/running_fpga_vi_on_emulator/ 

"Understanding Simulated Time on the Host

If you use certain FPGA resources and you execute the FPGA VI in simulation mode using simulated I/O, the resource uses simulated time instead of real time. Simulated time might be faster than real time depending on the number of events that occur during the simulation. For example, if you add a Wait (Simulated Time) VI to the block diagram and set the delay to 1000 ms, LabVIEW does not attempt to delay one second of real time. Instead, LabVIEW delays as long as necessary before executing the next scheduled action in the simulation.

The following resources use simulated time on the host:

• While Loops
• Single-Cycle Timed Loops
• Wait (Simulated Time) VI
• Loop Timer Express VI
• Tick Count Express VI
• FIFOs, except DMA FIFOs
• Wait on Occurrence with Timeout in Ticks Function
• Interrupt VI, when Wait Until Cleared is TRUE"

I am not too sure on your specific problem but can you possibly post your code? Have you got excessive amounts of any of these or massive wait times? Hopefully this link above helps.