FPGA synchronisation loops

[rra]

Hello fellow LabVIEWERS ,
I have a question about synchronisation of loops within a FPGA (compactRIO
PXI-7831R) device.
I have 3 loops running independant from each other, but still I want them to
execute synchronised to the FPGA internal clock (40 MHz).
I possibly could use the "single-cycle timed loop" but then a lot of VI's
are not available.
B.t.w. I use FPGA sw module 7.0 for LabVIEW 7.1 on a windows platform.
Any ideas/examples how to achieve this. ?

Also another question:

The FPGA target offers the ability the set the FPGA sample clk to
40,80,120,160 and 200 Mhz.
No slower sample freq is available , but the higher frequencies generate
compiler errors when the FPGA code is
compiled.
What good are these sample clk. settings ??

Thanks in advance ,

René Ramekers

[andre.buurman@carya]

Hello René,

The LV User manual gives some help. Use "Timed Loop (FPGA Module)" as the search term in the help and select topic 7, which has to same title.

The talk about a single timed loop.

The single timed loop can contain the function "Set occurrence". Your loops can be synchronised by waiting for that occurrence in all the loops that you want to synchronise.

I hope this help,

Kind regads,

André Buurman @ CARYA

[andre.buurman@carya]

I forgot something.

I used the help of LV8.

André