FPGA: unpacking U32 into bits causes fan-out timing violation

[Intaris]

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@Intaris wrote:

Also adding shift registers in correct strategically chosen places will help.

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D'oh, I meant feedback nodes.... Sorry.

[itayshom]

Thank you all for your help. I changed the scheme a bit and  got rid of the subtraction and comparison, which eliminated the timing violation.

I have also posted another question concerning this code:

http://forums.ni.com/t5/LabVIEW/FPGA-Does-priority-have-an-meaning-with-FPGA-running-VI/td-p/2892278