FPGA

[DaveCl]

Hello,

I am trying to make a case structure run only one time whenever it is called. I have tried various attempts using a feedback node but I can't get it to work. First call won't work because the inner case needs to run whenever the two outer cases are true. No event structures can be used in an FPGA. This really has me stumped. I must be overlooking something really obvious. Attached is the frame work which I am using.

The ultimate goal is to have a subVI in the inner case structure run only once. Any suggestion on solving this would be greatly appreciated.

Thank you,

Dave

[crossrulz]

If we know everything else that is happening in this VI, I'm sure we could come up with something better.  But here is what I quickly came up with.  It is dependent on the Use Default Value If Unwired output tunnels (which will output a FALSE in the unwired cases) and a shift register.

[DaveCl]

crossrulz,

Thank you for such a quick response.

The VI that will be in the inner case structure controls digital outputs on a 9375 module. The inner false case will also have a similar subvi as the true case that will need to be executed only once.

Based off what you suggested I am going to try using integers in place of Boolean controls for the inner case. Earlier, I was toying with the iteration counter with a feedback node, but I didn't get that working either.

In short the false and true cases of the inner case structure will each have subvi's that only can be run once.

Dave