Facing an Issue which compiling FPGA VI

[hemanthsurya99]

Hello Team,

I created fpga.vi. block diagram consists of simple adder circuit. whenever i am compiling i am getting compilation error. can anyone help me in this regard?

Thanks

[ZYOng]

Post your full project and your compilation results. Otherwise, we don't know what's the issue.

[hemanthsurya99]

ERROR: [Opt 31-67] Problem: A LUT6 cell in the design is missing a connection on input pin I0, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: GpioOutEnMux0.
Resolution: Please review the preceding OPT INFO messages that detail what has been trimmed in the design to determine if the removal of unused logic is causing this error. If opt_design is being specified directly, it will need to be rerun with opt_design -verbose to generate detailed INFO messages about trimming.

The above picture is my block diagram. I have created only FPGA.vi nothing more than that and i am trying to compile it.

[Bob_Schor]

What hardware does this use?  Inside what "device" (be as specific as possible) is the FPGA located?  We need to see the Project file (.lvproj) that contains this FPGA code.

Bob Schor

[Terry_ALE]

Also, can you compile a shipping example?

[hemanthsurya99]

Hardware: PXIe 6592R
FPGA: Kintex 7

[hemanthsurya99]

Where can i find shipping example?

[hemanthsurya99]

please check .lvproj file snap

[Terry_ALE]

File >> Create Project

Look for 6592 projects

Help >> Find Examples (search for 6592)

[hemanthsurya99]

I didn't find 6592R device itself in NI EXAMPLE FINDER