FlexRIO Compilation Error

[ozan_icin]

Hello,

I wrote an FPGA code for FlexRIO-7975R which has multiple p2p fifos,DMA fifos and target scoped fifos. The compilation fails during the "synthesizing" step after a few hours(sometimes it takes more than 15 hours). There is no error code or descripiton for the error. It doesn't create "the estimated the device utilization report" or does not give timing violation error.I have created multiple build specifications for the same code and tried many times(I tried both the compile cloud and local server) but I couldn't succeed. You can see the screenshots and xiling log in the attachment.

I would appreciate for a suggestion.

Thanks,

Ozan

[Peter_Heseltine]

Looks like the xilinx compiler is crashing out. Are you sure the compilation PC has enough resources memory etc?

[ozan_icin]

In fact I am using Compile cloud service. I decreased the size of all fifos as much as I can but it didn't work again.

Sometimes I may also get Internal software Error on the same step.

[Peter_Heseltine]

How many P2P links, DMA channels are you using? I have created FPGA vi's successfully with multiple P2P and DMA links with no problem. I would suggest trying to isolate the area of your code that is causing the problem. Try using a diagram disable box to eliminate areas of code and recompiling till the error goes away. It doesnt matter that it will make your FPGA non-functional but it should enable you to isolate the area thats causing the issue. Also check the properties of all your DMA's and P2P links to make sure they have sensible values. It also helps sometimes to try using Rebuild instead of Build.

[ozan_icin]

Hi Peter,

I realized that there was a case on the code such that same DMA is being written twice in the same cycle in SCTL. I think that was the source of the error. I changed the algorithm and I can compile it now. 

Thanks,

Ozan