Hi Experts,
Quick question regarding the DRAM on a FlexRIO board. Is is possible to use it (configured as a CLIP FIFO) not inside a SCTL?
My application worked fine when the memory writes and reads were in SCTLs (separate loops for these), but for various reasons I need to use a plain old While loop on the read side. The compile does not show any errors, but the application is giving strange errors like lots of data is being lost.
