Have problem with downloading the FPGA bitfile of the ethercat expansion chassis

[Gevorg]

Hi all,

I'm using a NI 9025 cRIO communicating with 4 NI 9144 ethercat chassis. The 9144 chassis are working on hybrid mode. When I build the FPGA VI of the ethercats, download them everything is OK. But when I want to download the same bitfile again (which is already built), it asks me to build it again (the buiding process takes about 1 hour). If I don't build it again the code doesn't work properly. I'll appreciate if anyone can help.

Regards.

Gevorg

[jzhou]

Hi Gevorg,

LabVIEW requires a rebuild when it finds the bitfile that you downloaded to your FPGA target doesn’t match the configuration in your LabVIEW project. This could happen when you add/move/remove C-series modules, add/remove/change User-defined Variable (or change its properties), update your FPGA VIs, etc. Rebuild will make sure your changes take effect.

For NI 9144, one way to skip the rebuilt is to download from the Online State Panel: right click the slave item in the LabVIEW project, open the Online Device State, manually switch the 9144 to Bootstrap mode, click “Download Firmware” and navigate to the folder where you keep your bitfile. In that folder, you will find a .foe file and you could simply download it to your 9144 chassis. This foe file is generated from your bitfile so the functions and logic are all the same just with different format.

However, we usually do so when we duplicate the system, i.e. to multiple 9144 chassis with exactly the same hardware set and configuration. In your case, we would still suggest you to rebuild your bitfile in order to make sure all the code works properly.

Hope it helps!

[Gevorg]

Hi jzhou,

Thank you for your response. I've tried to download the .foe file and it didn't ask for building. But after a few seconds after running the project an error accurs on the ethercats (the red LED is blinking) and the CPU usage is 100%. The strange thing is that I didn't change anything in the FPGA VI, and it says that the bitfile doesn't match the FPGA configuration. It may be a bug I think. So in any case I have to build it again.

Regards,

Gevorg

[ZX81]

BTW, somewhere between LabVIEW 2012 and 2019, "Online Device State" moved.  It is now Project/<cRIO>/Chassis/<FPGA>/"RIO Device Setup...".  And I suspect you have to connect first (Project/<cRIO>/"Connect"), but didn't experiment.

I get the 'bitfile signature does not match' all the time when it shouldn't.  I just got it, and love your work-around.  Thanks.

Today, I did the FPGA build (knowing the .vi hadn't changed, but had to anyway).  It took 5 tries to get it to send to the server successfully (the typical C:\NIFPGA\compilation folder corruption bug; why can't they fix this one???).  Finally, it started, and I went to lunch.  When it was done, I tried download 3 times; no  response (no acknowledge or fail; why can't they fix this, either???).  Tried cRIO's real-time program, and saw the FPGA wasn't updated.  Tried download again, and it said the bitfile didn't match.  I didn't change ANYTHING.  All I did was Operate/Remote to observe results.