I made a post about this four years ago, and am frustrated to come back to the topic to realise that the help/documentation hasn't improved at all. Here's the old post I made.
https://forums.ni.com/t5/LabVIEW/Using-Host-memory-buffers-for-data-transfer-between-Host-RT-and/m-p...
Are there any real examples of how to use Host memory buffers to communicate between an RT host and FPGA target? In this particular case I am using the Sbrio-9651.
Host memory buffers are appealing, as it appears that they are the only host to target communication method that exposes a pointer-like interface (EDVR), which allows one to selectively write to some parts of the shared memory whilst preserving others.
For example, if seeking to write to a digital output bank on a target, I have only encountered suboptimal alternatives;
- Create individual controls on the FPGA front panel for every digital output, which then need to be explicitly addressed individually (and this can't be done dynamically or arraywise)
- Use an array control, which needs to be written in its entirety, so if one output is to be modified, the whole array must be read, modified and rewritten to the FPGA
- Use a cluster, which has the same problem
- Use a FIFO, which also has similar issues
I seem to be able to write to some kind of memory space that can at least be read on the RT, but I am having no luck reading that memory on the FPGA. It's completely unclear why the write method needs to be used on the FPGA when seeking to accomplish host to target communication, or what the various inputs actually do (input valid, ready for output, etc).
Have host memory buffers been half-implemented and just relegated to a quiet death?
