Host to FPGA DMA fifo timing error

[rahulvinus]

Hello 

I am new to labview .... and wanted your help on an issue

I want to tranfer data frm the host to the fpga and then to the Analog output module...I have attached my VI.

there has been a timing violation error when i compiled the vi .. mainly when the data is transfered from the host _to_the_fpga(FIFO4)  to the local FIFO (FIFO5).

All the loops are running at the IO module clock i.e the rate at which DAC and ADC CLIP is communicating.

I am attaching the image of the block diagram...

[natasftw]

Posting a picture is almost useless.  We see very little of what you're actually doing.  In addition to this screenshot, you've got a host VI.  YOu've got a project.  You've got FIFO settings.  Likely, you have even more.

What does the timing violation actually say?  You've provided absolutely nothing in terms of the actual error.  It cannot be "mainly" taking place when things are transferring as you're failing a compile.  That means you never get to the point the code actually runs.

Why would you want to read from FIFO 4 and immediately write that to FIFO 5?  Why not just write to FIFO 5 in the first place?

Is this a FlexRIO bit of code?  If so, what's the module you're using?  They don't all have the same.  Telling us it runs at the rate the IO Module provides doesn't really tell us anything.

You need to help us help you.  As it stands, we need to guess about 80 things related to your question to give an answer.  You're not going to get much that's productive until you give us details about what you're working with.