How can I do it better ?

[charlie87]

Hello,

I am new in LV FPGA and I am working on a project which I need help with. I implemented SCTL and pipelining according to manuals and tutorials I had found. However I would appreciate a view of someone who is well experienced in FPGA programming and willing to help.

I do not want you to do a code. Just check it and when something significantly wrong, please tell me or suggest some solution.

[nathand]

Sorry, there's just too much code here with too few relevant comments to be helpful.  Does this code work?  Does it compile?

Also, do you understand the reason for pipelining?  It looks a little bit like you read something about pipelinining and tried to do it everywhere without fully understanding where it's necessary and appropriate.  I suggest that you start by making the code as simple as possible to do what you want, and then start pipelining - one step at a time, not all at once - if you cannot meet your timing restraints (during the FPGA compile).

[Ardent]

Hi Charlie,

how about trying LabVIEW FPGA Module Training? It is free and I would consider it a rather good resource, if you are basically starting with cRIO development.

[Ardent]

Hey Charlie,

Looking through your code and seeing no real time, nor host application, I would also recommend taking a look at the LabVIEW Real-Time Module Training and possibly the NI LabVIEW for CompactRIO Developer's Guide. Good luck with your application!

If you run into something, do not hesitate to ask!

[charlie87]

thanks guys for answer and your opinion.

You are right, I have been trying to implement pipelining acc. to  developer guide for cRIO. I understand the reason and the basic princile of pipelining.

However when I have seen the NI course I think I was misleading. (I read it already before, but in a short time and I forget to check it again) I put feedbacknode between all two functions I have in code. Now I think it is incorrect. I should put it between bigger parts of code which are each able to finish in 1 tick. Am I right ?  Then I would save some space (from feedback nodes) and decrease latency...

Host vi is being done by my colleague....

[charlie87]

Actually, I was doing pipelining acc. to this picture and idea from developer guide

I am not still sure about using high throughput math as it is in the example. How it can halp me or not ? I was said that HTM block should not be used but in all manuals it is writen that HTM block are faster and take less resources...

[charlie87]

I tried to remove all feedback nodes for pipelining and after compilation I got this message : 

LabVIEW FPGA:  The compilation failed due to timing violations.

I suppose it is because pipelining is missing. Am I right ? 

I know that it is probably obvious for all of you but I am learning and I have some suggestions and opinions which I need to investigate and check.

[nathand]

Pipelining is one way to resolve timing constraints, but it is not the only solution.  Is the code that's causing the problem inside a single-cycle loop?  If so, you could take that code out of a single-cycle loop and let the compiler figure it out; it will cost you more FPGA resources and you won't have as much control over timing, but that might be fine so long as it still compiles succesfully.  You can also attempt to simplify the logic or reduce the precision of the fixed-point values.

If you don't know that you need the high-throughput math functions, then you probably do not need them.  They're useful for very-high-speed computations, and it looks to me like you're not that concerned about exactly how many ticks your algorithm uses. 

[charlie87]

I changed the code to get better performance. I put all signal preprocessing and processing into SCTL to save resources and use pipelining to get correct timing.

Please check the code and suggest your opinion. Especially about pipelining and SCTL idea. There is Main.vi

[nathand]

Looks better to me - putting as much computation as possible into a single-cycle loop is the right idea.  However, have you tested the algorithm?  (You can, and should, do this on your PC with simulated data before compiling the FPGA.)  I think I see one problem: you never change the index value.  You set it to 14 and it never changes.