How can I do it better ?

[charlie87]

You were right about bad indexing....I did a mistake and connected incorrect wire. 

I tested the subVI but not the whole algoritm....

I have real data in txt file. Is it possible to use this data for simulation on PC ? 

[nathand]

Yes, there are two ways you can test with data from a file:

1) Write a VI to simulate the inputs.  See "Creating Test Benches to Debug and Test FPGA VIs" (also in the LabVIEW help)

2) Create a copy of your VI and modify it so it reads from the file instead of from the FPGA IO nodes, then run it on your PC instead of on the FPGA target.

[charlie87]

Well.  I managed to do some benchmarktest and run the system with real data loaded from txt file.

I found some problem and I do not have idea how to solve it.

In the computation in SCTL I want to calculate derivation for some channels and integration for some other channels. I am using standard trapezoid formula. I am processing data in interval +-1 with precision 0,0001.  For sampling frequency e.g. 20k and small difference between two following points (about 0,001)  I am getting very low number about 10e-6. When I desing the project I use precision 0,0001 for all calculations so I am getting zeros. When I want to design the processing with higher resolution then I am over the slices count in FPGA. ............. It makes me sence, because I want to use higher number and it takes more gates however..Is there any way how to solve this ? I heard something about DSP ... 

[nathand]

Do you know what range of values you expect to see?  If you know that your values will always be in a narrow range, you can configure your fixed-point values to use a small number of bits but shifted so that they provide enough resolution within a small range.  You can actually configure a negative integer length.  For example you can configure an 8-bit value with an integer length of -4, resulting in a range of -0.031 to +0.031 where each bit represents a change of about 0.0002.

Another possibility is to attempt some kind of dynamic scaling, where you scale the inputs to maximize the available resolution prior to doing any processing, then rescale the results.  This takes a bit more work but if you're going to work with a wide range of possible inputs and have limited resolution it might be necessary.

[charlie87]

I have 4 data types. I think I can know data type before processing. What do you think about the solution ? I think dynamic scaling would be best, but not sure about the ideas, you mentioned

[nathand]

I have no idea what your graphs are supposed to indicate, but if you know the range of values that you expect to receive in advance, you should maximize the available resolution either by adjusting the fixed-point settings or by scaling the values.  It is generally much more efficient to scale by a power of 2 than a power of 10.

[charlie87]

I think I got the idea. I do what I can. Thanks

[charlie87]

Hi,

I finished the fpga code and now I am testing it in the HW. however something is wrong.

I open new thread so please check if you are involved

http://forums.ni.com/t5/LabVIEW/timing-fpga/td-p/2055486