How do I maximize FPGA AO rate on 7852R

[manliff]

I am trying to maximize the AO rate for the FPGA -7852R.  The specified AO rate is 1MS/s.  Or in terms of the internal 40MHz clock 1MS/s should be 40 ticks/sample.  (on maximizing the AI I achieved 54 ticks for a specified rate of 750kS/s, which is as it should be)

I am using two loops and FIFOs with an "occurrence".

In the while loop I have a case structure with the FIFO and I/O (AO) node controlled by an "wait on occurrence"

In a SCTL I have a FIFO of depth of 20 samples where the loop writes every certain number of cycles, user settable.  In the SCTL, I have the FIFO Timed Out connected to an indicator. Eg. So every 45 ticks or loops it writes a sample to the FIFO and sets the occurrence.    At 45 ticks I get no Timed Outs indicated from the FIFO; that is the FIFO is not full or overflowing. At 44 ticks the Timed Out indicator goes green indicating the FIFO overflow; that the AO loop is not keeping up.  I am hoping that I can find some code method to reduce the AO rate to 40 ticks without overflowing the FIFO. (the SCTL loop is just a AO data generator that outputs a simple data scheme for AO. This code is just to study AO rate methodology. I learned in my AI rate study that the AI while loop is sensitive to what else is going on in the loop)

I would like to minimize the latency between a set occurrence and wait on occurrence for the AO as I will not have periodic AO updates. 

Also in general I would like to do 40 tick AO period with a FIFO transfer between loops; can this be done? Is there something other than an occurrence to do it?
In general how does one achieve the 1MS/s specified AO rate?

Does the set occurrence and wait on occurrence take a fixed number of ticks?

thanks 

John K

[Ruhmann]

You should be able to meet the expected rate  if you use an 80 MHz clock as your top-level clock instead of 40 MHz.  I'm not sure if you can reach 1 MS/s using a 40 MHz clock.  Also, you shouldn't need to use occurrences.  Instead, time the loop with the IO Node using the loop timer.  Use a timeout longer than your IO loop on the write FIFO method to make sure it won't overflow the FIFO as long as the IO loop is running and consuming elements from the FIFO.  Here's a code snippet showing the VI I used to test all this.  I'm measuring the ticks in the top loop to make sure that the desire rate was being met.  It works fine at 80 MHz.