04-09-2013 06:17 PM
I successfully downloaded and compiled "daqmx_pwm_examples.zip"
from http://www.ni.com/white-paper/2991/en
and executed it in LabView. I know it works because the oscilloscope correctly displays a pulse waveform with the desired frequency and duty cycle.
I noticed while the program is running, if I decide to change the duty cycle it dynamically updates the pulse wave form on the oscilloscope. However, if I change the frequency while the program is running it does not update in the oscilloscope.
I think the reason is because the duty cycle is hooked into a "shift register" whereas the frequency is not.
I have attempted to hook up the frequency into a shift register as well, and I was wondering if i could get some advise with regards to simplying or correcting my back panel wiring diagram shown here:
http://i.stack.imgur.com/j6tdP.jpg
I would greatly appreciate all / any advise.
Thanks.
Solved! Go to Solution.
04-09-2013 06:55 PM
You only need one instance of DAQmx Write; it has inputs for both Frequency and Duty Cycle. Delete the additional one. Add an OR on the case structure condition - you want to execute the write if the Duty Cycle has changed, OR if the Frequency has changed.
04-10-2013 02:36 PM
Hi Nathand -
I have updated my wiring diagram based off of your suggestion: http://i.stack.imgur.com/p9g4u.jpg
Is this what you were referring to?
If not, could you please comment?
Thanks.
04-10-2013 03:39 PM
I think that's the right wiring, but it's hard to tell since you show the false case where nothing happens. You could clean it up a bit by removing excessive wire bends and keeping wires running left to right.
No need to upload to a third-party image hosting site, the image hosting on this forum works fine and you can upload directly. Even better would be to attach your VI instead of a screenshot.
04-11-2013 03:52 PM
HI Nathand -
I have uploaded the VI as well as an image of the back panel.
Please let me know what your thought are.
04-11-2013 03:54 PM
Still some ugly wires (particularly the error wire that loops back under the case structure) but the logic looks fine. I'm not really sure what you're asking - are you still having a problem with it, or does it work as you expect? Did you test it?
04-11-2013 05:54 PM
Hi Nathand -
I just tested it right now and it works perfecrtly using the diagram below:
.
I cleaned it up using the "Cleanup Diagram" button. I uploaded the VI as well in case anybody else needs it.
Thanks for your help.