How does the target scoped memory in FPGA works??

[charansai]

Hello there,

I have some basic questions about target scoped block memory item in FPGA. I am using NI myRIO 1900 with LabVIEW 2015.

Is it possible to access the target scoped memory values, I know a way where I can access through DMA FIFOs on RT side.

But for my application I will be applying LMS on some input audio data where the LMS coefficients(Target scoped memory) will updating all the time and when I stopped the while loop or after I stopped the VI, I have to access this memory in another VI to use it for further processing.

I tried to do this but I kind of getting a feeling that ''these target scoped memory items are getting reinitialized to default values each time I stop the VI''

Is it so?? 

In the project attached below, I am trying to access ''FXP LMS e'' target scoped memory values.

Please suggest me how to do it.

Thank you.

[charansai]

Is it possible to extract the values of Target scoped memory after the VI that is using that Memory has been stopped ??

When the Target scoped memory will be re initialized to its default values ?

Thank you.

[Jacobson-ni]

I haven't taken a look at your project but you cannot directly read from FPGA Memory items from your Host VI. Usually you will use a DMA to transfer the data up from the FPGA but if you are only doing a few transfers and there aren't that many data points to move you can get away with using read/write nodes. The FPGA High Throughput Developer's Guide does a good job of going over data transfer mechanisms starting around page 82.

http://www.ni.com/tutorial/14600/en/

---

@charansai wrote:

Is it possible to extract the values of Target scoped memory after the VI that is using that Memory has been stopped ??

When the Target scoped memory will be re initialized to its default values ?

Thank you.

---

I thought memory was only re-initialized when you power cycle the FPGA or download the bitfile again but it is probably better to just read the whatever data you want before stopping the application.

[charansai]

Hi,

Sorry I was not clear enough !

My problem is not with transfering target scoped memory data to RT(Host) side but I am struggling with accessing those values on FPGA(target) side.

What I mean simply is, I have FXP LMS sub VI which I am using in another VI where the LMS will be operated on some data, I am storing these coefficient values in Target scoped memory.  Now if I try to use these stored coefficient values in another VI, I am getting 0 as output. My guess is that the Target scoped memory values are getting re initialized once the 1st VI has been stopped. 

Is there any other way where I can use one VI values in another VI, values are of size 128 ?

Thanks for link of FPGA high throughputs guide, I went through it but could not find anything related to How target scoped memory works .

Thank you. 

[Chrisi93]

Hi charansai,

Do you use the Simulation Mode?

if yes, take a look at this help:

Communicating with an FPGA VI Executing in Simulation Mode (FPGA Interface)

http://zone.ni.com/reference/en-XX/help/371599L-01/lvfpgahosthelp/comm_fpga_dev_comp/

Do you tried it also on FPGA?

[charansai]

Hey Chrisi93,

I did not use simulation mode, I was actually implementing on the FPGA.

[charansai]

I think this is my answer to my question. To state it properly

I found target scoped memory will be initialized each time the working vi stops i.e essentially it will also work like VI scoped memory, only difference between both being taget scoped memory can be used in several instances(VIs), any changes made to these memories will essentially influence all instances, which is not the case for VI scoped.

So I have to access the values before stopping the VI as Mr.Jacobson has suggested.

Thank you.

[Dragis]

Hi, @charansai, can you give more details on exactly how you are using the memories within your application?

I'm a little confused by the statements about VIs stopping and starting and the values of Memories between VI runs. Are the VIs that are stopping and starting free-running VIs in a loop in a single FPGA application? Or is the communication being attempted between two separate FPGA instances?

Generally, since the introduction of VI-Defined resource references, it is now best practice to pass references to resources used for communication between VIs. The Target-Scoped resources are there for legacy applications, but for reusability and maintainability of code, anything new should use references if possible.