How many times can an FPGA code be dumped in R-Series card?

[kwan]

Hi,

I am developing a test system, where in I am using an FPGA R-Series card. My code is too huge that it is consuming more than 100% of the available slices. So I thought of dividing the code into 3 individual FPGA VIs & dump the required bit file whenever it is required.

I want to know are there any limitations for frequently dumping the bit files into R-Series cards? How many times can I dump the bit files?

Thanks in advance...

[Ruhmann]

Downloading a bitfile to the FPGA shouldn't cause any wear on the hardware.  An FPGA is a lot lilke RAM in your computer.  The only problem I see with your idea is that it takes a few hundred ms to download.  So, if you're OK with that delay, your application and hardware should function fine.

[FeilongLin]

That's a good question I want to know too.

As I found out in the http://digital.ni.com/public.nsf/allkb/91DE0C3B7740C287862574D300646369

we can write the bit file to the flash memory approximately 100,000 times. 

Can anyone told me the difference between write and download bit files to FPGA?

Also, in the "configure open FPGA VI reference" property of  "open FPGA VI reference", we can download bitfile very fast in here, does this reduce the life of flash memory?

Thanks.

Feilong