How to Delay Data with Handshaking?

[ejesse]

I have been working on an FPGA project, and I'm wondering: What is the best way to delay data alongside handshaking operations?

For example, say I have inputs A, B, and C inside a SCTL. A and B are inputs to a high-throughput multiplication block with a latency of 10 cycles. My instinct is to put in a feedback node with an enable terminal wired to the ready for output terminal. However, I've found that the high-throughput math (at least in simulation) can continue to push data through the pipeline when Ready for Output is false. Thus output X can be valid while Y is not.

One of my attempts to solve the problem is by separating out the input valid signal into its own feedback node and wiring a true constant to the multiplication input. However, this requires some extra logic and basically ruins the handshaking as Ready for Output becomes more of an enable signal and Ready for Input is basically worthless.

I've considered a number of alternatives, but none of them quite fit the bill. In this example, I could multiply C by 1, but that's not always possible and I'm worried about the extra DSP resources that would use. I've considered using a FIFO to be read when the output is valid, but I'm worried that the FIFO's complexity will have a high resource cost.

So my question is, what is the recommended way to match these outputs while retaining the handshaking?