How to implement FPGA to FPGA DMA "like" communication?

[Southern_Cross]

All,

I have an application whose logic cannot fit on a single SOM (sbRIO-9651). Fortunately, I have the freedom (space, weight, power) to add a second SOM. I'm looking for the best approach to share data between the two SOMs such that they act "as if" they were one big FPGA. Meaning, data from each SOM needed by the sister SOM is communicated with "minimum" latency. 

For the sake of discussion, assume that I have about 48 lines available on each SOM to acheive the bi-directional communication. Also, assume that the data being shared in each direction had a predefined structure that would not change. So, a blob of data needs to be sent in each direction and would be interpreted appropriately by the receiver. Lets also assume that we're trying to maintain a 500kHz clock rate on the processing loops in each respective FPGA consuming/using the data. I don't yet know how many bytes of data that need to be shared so lets assume it's on the order of ~150 bytes of data going in each direction each iteration.

Ideally, I'd like a resource like DMA that could go between the two FPGA devices but to my knowledge this is not possible. I could use something like SPI or I2C but I'm concern that they would be fast enough. Are there alternatives (e.g. some parallel port like prototcol) that can be considered? Is there existing example code for these protocols?

Thanks.

[Sam_Sharp]

SPI would probably be what I'd be looking at - you should be able to get pretty fast clock rates and it's a simple protocol to implement on the FPGA. You can go as fast as your FPGA clocks will allow and the electrical connection (depending on length/quality of the connection). You could also implement a parallel interface with 4/8/16 data lines and a clock line.

I'd also question whether or not you could optimise your FPGA logic to fit the code onto a single SOM if you were to optimise - I don't know your LabVIEW/FPGA knowledge level but there are lots of techniques which can save you a lot of FPGA resources. There's a whole heap of really useful/advanced FPGA knowledge in this guide: http://download.ni.com/pub/gdc/tut/labview_high-perf_fpga_v1.1.pdf

[Southern_Cross]

Thanks Sam. I'm still optimizing but am starting to see the likelihood of not fitting, so, I'm starting to investigate other options in the event that further optimizations don't succeed...

[Jacobson-ni]

There is a pretty decent FPGA API for SPI that would be a good starting point.

http://www.ni.com/example/9117/en/

There is also a previous thread that discussed how to get that working on the 9651.

http://forums.ni.com/t5/Industrial-Communications/LabVIEW-FPGA-SPI-with-NI-9651-dev-board/td-p/30764...

Not sure of how optimized it really is but it will probably be better than just starting from scratch.