How would you tide up these cables?

[antoniobeta]

Hi! I have been reading the forums for a couple of years, this is my first-time writing.
I am currently working (professionally) with LabVIEW every day and now I am studying for my CLD exam. Since I started studying, I have been questioning the location of every wire I lay out and would like some advice on how you would lay out the cables on the VI I have attached.

Thanks to all!

[Yamaeda]

That works fine. The operations are so small and fast you can do them sequentially and i prefer to use Icon mode on the Bundle cluster, but that's personal preferrence.

[antoniobeta]

Thanks for the answer. Since I started looking for how the CLD gets corrected the wire management chases me. Maybe I am being paranoid.

[Yamaeda · Accepted solution]

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@antoniobeta wrote:

Thanks for the answer. Since I started looking for how the CLD gets corrected the wire management chases me. Maybe I am being paranoid.

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You're being paranoid. 🙂 I have some OCD regarding wires sometimes, but just avoid unnessasary bends and crossings (as you've done) and it should be fine.

[billko]

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@Yamaeda wrote:

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@antoniobeta wrote:

Thanks for the answer. Since I started looking for how the CLD gets corrected the wire management chases me. Maybe I am being paranoid.

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You're being paranoid. 🙂 I have some OCD regarding wires sometimes, but just avoid unnessasary bends and crossings (as you've done) and it should be fine.

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I think they rely heavily on VI Analyzer, so this isn't so paranoid.  I would consider the proposed BD excellent, but I would try to make the branching error wires not cross the constant wires, for example.  IMO it makes it uglier and less readable, but VI analyzer will call them unnecessary and you could possibly be penalized.

[Kyle97330]

My own personal preference is that if you have a choice between making two different wires straight, the error wire should be preferred as the straight wire.  So in this particular situation, I would have made the error wire leading to the "register for events" node straight, and bent the event reference leading to it instead.

I do this so that there's one sort of "central line" to follow showing all the operations that occur sequentially down the middle of the VI, and all calculations that feed into that line are above and below it.

The branching of the error wires is something I generally would not do unless the operations are time sensitive and need to be done in parallel, or if the operations are vital to complete even if one of the other ones has an error in it.  I don't think either of those apply here, but it's hard to be certain without knowing the context of the VI.  There is a small possibility you could get dinged for that.

[Yamaeda]

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@billko wrote:

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I think they rely heavily on VI Analyzer, so this isn't so paranoid.  I would consider the proposed BD excellent, but I would try to make the branching error wires not cross the constant wires, for example.  IMO it makes it uglier and less readable, but VI analyzer will call them unnecessary and you could possibly be penalized.

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The VI analyzer part is my understanding also. I do know they hit fairly hard on left wiring, which i lost a couple of point to due to different size/scaling between computers (there was no left wire on my screen). So, wire with extra room to avoid such issues, not Altenbach tight (as i like).