I think I might be doing something wrong when trying to log data with different FPGA loops speeds at the same time

[David99999]

I am trying to compare data from different loop speeds, specifically 3 phase power values such as voltage, power factor, etc. 

I am using a cRIO-9053 with 2 modules, NI-9238 for measuring current and NI-9244 for measuring 480VAC 60Hz. Both modules are set to 50ks/s in their properties.

What I've done is created an FPGA file that runs two loops in parallel, one is at the fastest loop rate of 20µs (50kHz). The other is at a slower rate, and in my examples the slower rate I'll be using is 250µs (4kHz). Again, the point here is to see how much worse the 4kHz sample rate data is to the faster 50kHz data.

I removed the code because I don't know if I can post it, but all my VI's I'm using have the correct settings for expected loop speeds and whatnot for each loop.

Here is a screenshot of my RT loop that does calculations and data logs. I will attach these VI's to the post.

What I don't understand is, that when I look at the data, both 20µs and 250µs values seem to ramp up (in terms of accuracy) at the same rate. Meaning, at the very beginning I have inaccurate data, which is to be expected from both loops. But I was expecting the faster loop rate to get up to accurate data quicker than the slower data. See graph screenshot below

Here is a graph when I've set the slower loop to be 32µs

Am I missing something here?

[santo_13]

I believe it is the signal ramp-up in the front end of the ADC and not the data sampled after the ADC, so the settling delay is irrespective of the loop rate.

[GerdW]

Hi David,

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@David99999 wrote:

I am using a cRIO-9053 with 2 modules, NI-9238 for measuring current and NI-9244 for measuring 480VAC 60Hz. Both modules are set to 50ks/s in their properties.

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Am I missing something here?

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General suggestion: don't access the very same AI channels from 2 different loops!

Accessing the same physical hardware from two (or more) instances will add overhead…

Suggestion: read the AI channels only in the fast loop and send decimated data (like every 10th sample) to your second loop!

Comment on your attachments:

• It doesn't make sense to add FPGA/RT code without the lvproj file, as that contains needed definitions!
• It doesn't make sense to add VIs with missing subVIs…
• It doesn't make sense to only add RT code, but not showing the FPGA code which is making problems…

[Terry_ALE]

Some good advice above.

I would add that the shipping examples for each module should be the basis for how you interface to the I/O. Other configurations may not have been tested.

[David99999]

Thanks guys.

One more related question. 

Is there anything special I need to do in order to ensure that the samples from each module were truly taken at the same moment in time?