Implementation of shift register using array

[falkpl]

Labview has shift registers aswell as feedback nodes for creating shifting data and creating a delay in itterative data, I would look at these structures.  The feedback node can even configure the z-delay.

[scps]

@altenbach

I was off the mark indeed 😞 The way I understood the interleaer-deinterleaver concept was all messed up.

There will be continuous input flow to the shift registers (which remain the same as on the figure)  which are initialised to 0's. So, if input is 512 bit long, output will be of length 512. Out of which 506 will be input bits and 6 0's. The final 6 bits of input will stay in the shift registers.

Similarly in the deinterleaver, we will get 512 bit output for 512 bit input. But here, in total 12 bits would have been appended. 500 of 512 bit input would remain.

Now working on implementing this model.

[scps]

Ok. I was able to implement both interleaver and deinterleaver as I wanted. I have attached both VI's here.

Thank you all for helping me out on this.

[Ben]

I'm late to the game and not offering a direct solution but would like to offer a little clarification.

Shift Register were implemented in machine hardware long before LV was ever invented. They are realized by using a set of flip-flops where each FF is a bit in the register (the collection of flip-flops). The output of low order bits can be clocked into the next higher bit using control signals and a clock pulse to perform the shift. The same functionality is available in LV when we use the Arithmetic Shift Left or Right. Shift register were used in modems to clock bits on to or off of a wire. They are also used to perfom interger multiplication since a multiply in binary is just a shift left.

Just wanted to explain SCPS's use of the term "Shift Register".

The use of that term Shift Register in LV becomes apperent when we drag down on a SR to get a history from the previous iterations.

Done with the trivia!

Ben