Importing Projects from FPGA 1.1 to 8.20

[Oli_Wachno]

Hi all,

today I eventually tried to import my FPGA project from 1.1 to 8.20. But unfortunately I got an error with a HDL node.
LabVIEW is telling me, that there were "unhandled outputs". So I checked my code, but I can't find anything. The "Check Syntax" button on the Code Tab of the properties dialog returns no errors? All outputs of the HDL node to the block diagramm are wired. Is there a secondary error that can cause this error message?

Thanks for your help!

Cheers
Oli

[jdigiova]

Please refer to the Known Issues for LabVIEW FPGA Module, 8.2 knowledgebase.  The readme shipped with a list of known issues before release.  This KB includes those issues as well as issues we have found after release.  The first issue found after release deals with the HDL node outputs not handled error.

http://digital.ni.com/public.nsf/websearch/9080C23D9C90BD17862571950072A8E0?OpenDocument

Regards,

Joseph D.

National Instruments