Initiate scan engine scan

[maherhome]

Hi,

We are attaching 3rd party EtherCAT slaves to our cRIO.  Is there any way to control the scan engine clocking so that we can reduce jitter (relative to an extrernal pulse) while communicating to the slaves?  Specifically, I would like to initiate scans when an external TTL pulse is received.

Thanks,

Steve

[REDS]

Hi Steve,

On the EtherCAT help file, if you search for "Distributed Clock", notice that there is a "Synchronize Input and Output" section that allows the "Synchronize Input Mode" to "Synchronized to distributed clock". This should help you out.

[maherhome]

I believe the ethercat distributed clock is an absolute time that is kept to a high precision amongst all ethercat participants (by calculating propagation delays).  This would, I imagine, allow multiple ethercat participants (e.g., a cRIO) to be able to perform an action at time (or interval) T where all ethercat participants agree when time T is (to some precision).

I don't think that will work for me.  I suppose I could use some of the delay options below to initially make the lag small between my external pulse and the ethercat sync, but since my external trigger's driving clock is not part of the ethercat distributed clock group it will undoubtedly drift and my lag will also drift.  I would have to dynamically adjust the parameters below, which doesn't seem reasonable.

At the risk of being repetitive, essentially I want to manually start each ethercat (ScanEngine) cycle by having it triggered by my (regularly occurring) external trigger.  My external trigger will accompany data that I want to distribute via ethercat and I want to keep the jitter and latency (moreso jitter) between getting the data and distributing it as low as possible.  Is there any way to have that sort of control?

Steve

[alcava.cr]

Hi, the scan engine works on the Real-Time side and to control the RT execution you need a timed-while loop. There are ways to synchronize this structure to external signals but on different platforms (like PXI using DAQmx), as mentioned here. Since this is not an option on a cRIO you can workaround by synchronize the IO directly through FPGA programming. I hope this helps

[maherhome]

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@alcava.cr wrote:

Hi, the scan engine works on the Real-Time side and to control the RT execution you need a timed-while loop. There are ways to synchronize this structure to external signals but on different platforms (like PXI using DAQmx), as mentioned here. Since this is not an option on a cRIO you can workaround by synchronize the IO directly through FPGA programming. I hope this helps

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Hmm.  My "external signal" is available in the cRIO FPGA.  I believe I can synchronize an RT Timed Loop by using a DMA FIFO from the FPGA to RT (I need to transfer the data to send over Ethercat at this point anyways so a DMA is fine). 

The problem I see is actually having modification access to the Scan Engine timed loop you're referring to (I haven't yet hunted for it) in order to add this synchronization (i.e., blocking FIFO read call).

I don't understand your workaround.  Perhaps you're quoting the workaround I've seen in an article about sync'ing a 9144 chasis with the controller cRIO.  I don't have a DIO board on our ethercat slave.

Steve

[Jesse_D]

Hey guys, 

I have done this before on a PXI chassis with a timesync plugin. I used a 6682 card to drive the PXI clock10 and syncronized the RT clock to the PXI clock10. Because the scan engine runs off the RT clock the two were synchronized. I have attached a project that shows the setup. 

I haven't done this on a cRIO before but if we can find a way to drive the cRIO RT clock off a signal the same idea should work. There is an FPGA timekeeper plugin but I don't know if it is what we want. Let me and Daniel see if we can find anything further on the issue. 

Assuming we cannot drive the RT clock off your external signal, we could just read the same clock signal on one of the ethercat chassis. The distributed clock functionality should guarantee that the cRIO master and ethercat slave are synchronized. You can use post processing to account for differences in the external clock and the cRIO RT clock. Can you tell us more about your system setup and requirements? How tightly do you need to be synchronized? 

[maherhome]

Thanks for the info ... heading on vacation for awhile so won't be able to process for a bit ...

Steve

[Jesse_D]

Hi Steve, 

When you get back we can discuss this further. At the moment I don't think that we have a way to drive the RT clock from the FPGA. We do have clock disciplining for PPS signals on certain cRIOs though. 

[maherhome]

Isn't the PPS clock disciplining applied to your absolute time clock (and not, for example, a driver for a Phase Locked Loop for the 40 MHz cRIO clock)?  Does the PPS somehow let you drive the RT clock (and Scan Engine timing) using absolute time?  Hey, microsecond cron jobs!!  

I"m concluding that I can't control when my data is sent over EtherCAT.  I'm hoping I can set the ScanEngine cycle time fast enough such that the resulting jitter in sending the data is acceptably low.  I'm just now getting the Linux EtherCAT slave up and running.

Steve

[Jesse_D]

Hi Steve, hope your enjoyed your vacation, 

While not driving the 40MHz clock, the PPS should be correcting something called the TimeSync engine. The Scan Engine should be run off the correction to the TimeSync engine and the Scan Engine runs the EtherCAT scan. So at the end of the day I expect PPS to discipline the Ethercat scan and timed loops (but not the base 40MHz clock). 

That still doesn't get us to the point of scans from a arbitrary signal though. We don't have functionality in the Ethercat engine to start a scan based off an arbitrary signal - it is dictated by the Scan Engine period.  

What can you tell me about your system? Will the triggers be cyclical? Can SDO communication be used? There may be something we can do if the signal is less of an arbitrary signal and can be used to discipline a clock.