Intermittent Signal Glitches in Square Wave Testing with NI-9222 and Issue with Digital Input Using NI-9402

[TurboGuu]

Hello everyone,

I'm currently working with an NI compactRIO system (cRIO-9066) and the NI-9222 module for high-speed analog signal acquisition. My setup involves sampling a square wave signal from a signal generator at a 100kHz rate, and the acquisition is handled using LabVIEW FPGA and the real-time system. I have encountered a recurring issue where the acquired signal shows intermittent glitches, as shown in the attached image. I think the glitches are not typical noise, but rather sharp transitions that resemble timing or synchronization issues.

Additionally, I’m facing another issue with acquiring digital input signals. I’m using the NI-9402 module for digital I/O, but so far, I haven't been able to successfully capture the digital input signals. All of my test signals are generated by a signal generator as TTL signals, with the pulse width defined by me. These signals are connected to both the NI-9222 and NI-9402 modules via coaxial cables

I’m relatively new to using compactRIO, so I’m not entirely sure if my program is optimized or structured correctly. Currently, I have based my program on the user-defined sampling example from the NI-9222 module documentation and made modifications to suit my application. My goal is to detect both analog and digital input signals within a given duration (e.g., 300ms). I've attached screenshots of my program and the actual code for reference. The Labview I am using now is version 2021 SP1 (32-bit). Could you please help me identify the possible causes of this issue, or whether there is a problem with my program? I'm open to any suggestions. Thank you.

[ZYOng]

Instead of using 3 separate FIFOs, I recommend using only 1 with channel interleaving. See shipping Hardware Input and Output >> CompactRIO >> FPGA Fundamentals >> Data Transfer and Storage >>Target to Host Transfer >> Interleaving Channel Data (DMA)

Your current method of polling essentially retrieves all available elements in the buffer. However, they might not return the same number of elements. To fit them into the same array, those channels with fewer elements will be filled with extra elements of 0 values, hence data mismatch.

[TurboGuu]

Thank you very much for your valuable insights. I will try the channel interleaving method. However, I have one more question.

For analog signal acquisition with the NI-9222 module, I am using the Generate I/O Sample Pulse method for sampling timing. However, it seems that the NI-9402 digital DIO module does not support this functionality. In this case, is there a suitable method to combine both digital and analog signal inputs into the same FIFO? Or is there a way to simultaneously acquire both analog and digital signals while maintaining time synchronization?

[ZYOng]

Not all C Series modules support User-Controlled I/O Sampling, to synchronize NI-9402 with NI-9222, place the NI-9402 I/O node inside the same loop with NI-9222. Interleaving the data from both modules will ensure you always read the same data points.

[Yogesh_Redemptor]

There are possibilities that the 'AI Signal' itself having glitches at generation point or measurement has the 'glitches'.

I would suggest, 

1. Check your wiring for 'Differential/AI Sense' or ground issue (Measurment Ground and Signal Ground).

2. Make sure your AI signal does not have any glitch in NI Max/ with some non RIO hardware. 

3. Use low pass filters to clear the glitches in the acquired signal.

Happy Debugging...

[TurboGuu]

Thank you all for your suggestions. In my LabVIEW setup, the NI-9402 DIO module does not support user-controlled sampling, so it seems I’m unable to collect digital signal inputs and analog signal inputs into the same FIFO using that method. As a result, I tried a more standard acquisition approach, as shown in the attached image.

This approach works well for the analog signals, and the waveform looks as expected. According to the NI example case note, this method might have a slower maximum sampling rate, but it should be sufficient for my application. However, the digital signal still isn’t being captured successfully.

The external signal generator’s three channels are outputting at the same frequency, and the pulse width used for the digital signal test should be the longest. In my program, I used Boolean to (0,1) for the digital signal and then converted it to FXP to send it through the same FIFO. Based on my understanding, the peak of the digital input signal should be 1, but it seems like the occasional peak is much higher than that. Any suggestions or alternative methods that could help resolve this issue would be greatly appreciated

[GerdW]

Hi Guu,

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@TurboGuu wrote:

I used Boolean to (0,1) for the digital signal and then converted it to FXP to send it through the same FIFO. Based on my understanding, the peak of the digital input signal should be 1, but it seems like the occasional peak is much higher than that. Any suggestions or alternative methods that could help resolve this issue would be greatly appreciated

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• You don't use the same FXP representation for that boolean value as is used for the AI channels…
  (I would use a Select node with two FXP constants with the correct representation.)
• You never reset the timeout condition in the FOR loop (uninitialized shift register!)…
• How do you read the data on the host side? Looks like a mismatch between the channels…

[TurboGuu]

Thank you for your suggestions. Based on your advice, I have modified the FPGA program as shown in the attached image. I may not have fully understood your suggestions, so I'm wondering if this approach is correct? Currently, the digital signal is still not being read correctly, and I am also encountering some random, strange signals.

There might indeed be an issue with the program on the host system. I have attached my host program for the reference.

[GerdW]

Hi Guu,

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@TurboGuu wrote:

There might indeed be an issue with the program on the host system. I have attached my host program for the reference.

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You should not read the number of existing elements in the FIFO, but a multiple of 3 elements (as long as you write 3 elements into the FIFO in the FPGA)!

There still is a coercion dot at the WriteFIFO node, so you should define the correct FXP datatype for the FIFO itself…