Is it possible to run 2 different FPGA loop speeds with the same calculations to compare data?

[David99999]

I just wanted to double check this before I waste time writing code.

I'm doing power calculations with the FPGA on a cRIO-9053, calculating things like watts, VA, power factor, etc.

I want to see how slow I can go before our values start to degrade.

Normally I run things their fastest at 50kHz, a 20us loop speed. But I want to see what the data looks like at 31.25kHz, 15.873kHz, 8kHz, and 4kHz.

Am I able to create 2 separate parallel loops in my FPGA file that both do the same calculations but at different loop speeds in order to compare the fastest loop to the slower loop?

[ZYOng]

Yes, you can have multiple while loops in a single FPGA VI. Depending on the requirement, you can use different inter-process communication method.

Another good practice is to expose the input of Loop Timer as a control so that you can change the loop time from RT VI without recompiling the FPGA VI.

[David99999]

Wow ok I did not know you can change loop timers on the fly. For some reason I was under the impression that did not work.

But, for my situation I don't think that will work in the FPGA, because the VI's I'm using for things like calculating the Mean Square require that you setup an expected sample rate and whatnot. Unfortunately they don't have VI inputs that can be changed dynamically.

[Jacobson-ni]

When you have two separate while loops I don't think you're able to acquire from the same I/O directly in both loops so you might need to have a separate parallel loop to acquire data and then your two calculation loops both read the latest value from some register.