Is this Aliasing

[lquarshie]

So I have an arbitrary waveform generator with a sampling rate of 150 MSa/s and an FPGA NI PXIe 7841R series board with a sampling rate of 200kSa/s. I know by the Nyquist theorem that if I want to get all data points without losing any, the frequency of my signal must be 1/2 of the sampling frequency (in this case, the FPGA).

At lower frequencies, say 1 - 10 Hz, I get a better-looking waveform on a Waveform Chart. However, at higher frequencies, say 1kHz, the waveforms are distorted on the Waveform chart and an oscilloscope. Is this an issue of aliasing? because 1kHz is less than 1/2 the sampling rate of the FPGA which is 200kSa/s. Also since I am trying to sample data points of a 1kHz frequency analog signal the loop timer value is calculated to be 1 ms. This loop timer value does not give a better waveform shape and I don't understand why.

I have tried to work around by playing around with the loop timer with the understanding that, the loop timer would affect the time taken for the loop to complete iteration which may also affect the number of data points that can be sampled in a tick. Is this understanding flawed? Can aliasing be solved by utilizing a FIFO with a specified timeout value?

The signal being sampled is a sine wave signal.

Please help. Screenshots of vi are attached.

[crossrulz]

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@lquarshie wrote:

Also since I am trying to sample data points of a 1kHz frequency analog signal the loop timer value is calculated to be 1 ms. This loop timer value does not give a better waveform shape and I don't understand why.

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You set the loop time to 1ms, which is 1kHz.  So you are actually sampling at 1kHz.  This obviously violates Nyquist.  Remove the wait entirely and then the loop will be limited by the maximum sample rate of the board (200kHz).  You will get a lot more data.

[lquarshie]

That is well noted.

I made the changes as suggested but still got the same results.

Does that mean I have no control over the data points sampled and resulting waveforms at high frequencies of say 50kHz which may be highly undersampled resulting in the sampled data being completely different from the original signal?

[mcduff]

You need to parallelize your FPGA loops.

1. Why are you writing and reading from a FIFO in the same loop?
   1. Write to the FIFO in the acquisition loop to stream to the RT side. If you need that value in the FPGA then read it from a parallel loop.
2. You are also try to use analog out in the same loop. Make another parallel loop, send the data to it and do your analog output.

FPGAs are meant to have parallel operations, break up your loop.

[paul_a_cardinale]

In addition to what the others have said, take note of the fact that when you construct a waveform from sampled data,

the result will contain frequency components above 1/2 the sampling rate, and all of that is noise (which can cause visible distortion on your waveform).  To remove that high frequency noise, oversample, then use a low-pass filter.

You can use the "Interleave 1D Arrays" function to oversample:

[lquarshie]

I used the FIFO as an alternative to getting enough data stored before reconstructing the waveform on the Waveform chart.

Also with the analog output that you see in the vi, it is intended to send the signal to an oscilloscope after processing.

[ZYOng]

I would recommend you to Measure FPGA Loop Time