Hi all,
As an extension to my other post Jenkins and LabVIEW FPGA - NI Community
The previous post deals with builds that could work if we detect a save in the (.lvproj) or FPGA VI, but I would not create a proper build if only the HDL is updated.
For reference, we use the CLIP Configuration Wizard to package legacy HDL. When I make an update to the HDL, the only way that I know how to carry forward those updates into the FPGA VI is to re-step through the CLIP configuration wizard to manually regenerate the (.xml) CLIP file.
Is there a way to automatically or programmatically regenerate the CLIP (.xml) file to allow us to fully automate this build process?
Thanks
