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LabVIEW FPGA CLIP Mandatory VHDL Signals

Hello NI Community,

 

I have a socketed CLIP that was working on a 7953 FlexRIO card. I recently upgraded to a 7972R FlexRIO and went to add my socketed CLIP to the card and it was grayed out for being incompatible.

I then used the CLIP Wizard to create a new .xml file to use with the new card and was instructed by the CLIP wizard to add the following signals to my VHDL code:

 

c100TdcDeassert : out std_logic;
Clk100 : in std_logic;
rTdcPulseWidth : in std_logic_vector(15 downto 0);
rTdcPulseWidthValid : in std_logic;
TdcAssertClk : in std_logic;
tTdcAssert : out std_logic;

 

May I ask how I should incorporate the above signals into my VHDL code?

These signals were not required on the 7953 card but are required for the 7972R.

 

Thanks,

Mike W

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