11-22-2023 12:35 PM
Hello,
I have created multiple FPGA bitfiles for different targets and dynamically deploy them to the cRIO, all of that works fine.
I have typedefs of "FPGA Interface Dynamic" which I use "Dynamic FPGA Inteface Cast" which I use on my cRIO app to cast the references to the appropriate type, that all works fine.
It would be convient for me to combine the behavior of "Dynamic Mode" and "Bind FPGA Host Reference to type definition" so that anytime I modify a bitfile, I could script the updating/importing of the typedef.
When you right click a FPGA reference on the block diagram and select "Configure FPGA VI Reference", you are greeted with this prompt which allows you to import from a .lvbitx:
Is this prompt available as a VI?
I would ultimately like to:
This is acheivable conventionally with just a few button clicks, but I would like to automate my entire build process.
Is this possible? Any suggestions?
Solved! Go to Solution.
11-23-2023 07:44 AM - edited 11-23-2023 07:44 AM
Hi Gryffin,
If you are familiar with VI scripting and a bit with XNodes, you may find what you want in folder:
"<LabVIEW>\vi.lib\rvi\ClientSDK\Core\Script\FpgaInterface\OpenFpgaVI"
Attached is an example script that does what you described. It uses some of the private FPGA scripting VIs to configure an "Open FPGA VI Reference" XNode from a bitfile. It then creates an indicator from its output and copy it to a type definition.
Regards,
Raphaël.
11-23-2023 08:11 AM
You can consider using LabVIEW FPGA Advanced Session Resources to load lvbitx dynamically.
11-23-2023 08:37 AM
Similar post about scripting an FPGA reference and the use of the LabVIEW FPGA Advanced Session Resources:
https://forums.ni.com/t5/LabVIEW/Script-FPGA-Reference/m-p/4245121
11-24-2023 12:18 PM
This is a very helpful VI but only acheives half on my desired goal.
If a change is made to the bitfile (add a control to the front panel), the output terminal of "Dummy Open FPGA VI Reference.vi" doesn't autoupdate (it breaks).
Is there a way to script/autoupdate the output of this VI so that it always matches the output of "Open FPGA VI Reference"?
11-24-2023 12:36 PM
11-25-2023 07:46 AM - edited 11-25-2023 07:48 AM
Thank you so much!
This is exactly what I was looking for.
I attach a slightly modified version which allows for dynamic file path entry of the bitfile, typedef to update, and the path to the "Open FPGA VI Stub" VI which should only contain a "Open FPGA Reference" (as seen below, pretty sure the constant and error feedback is unnecessary). LV2023 Q3
<Example of "FPGA VI Stub.VI">
I also closed all references and and wired error throughout, I hope this helps others in the future.
11-27-2023 06:05 AM