LabVIEW FPGA single cycle timed loop error: -61003

[GoKu25]

Hi Guys,

Compilation of my FPGA VI on a sbRIO 9651 SOM resulted in a error

code: -61003

Possible reason(s):

LabVIEW FPGA: You cannot include this function in a For Loop when the For Loop is inside a single-cycle Timed Loop

From this I understand that I can't use for loop inside a SCTL. But I have to send a arrays via DMA FIFO. Is there any solution for this. I am attaching a screen shot of the VI

Thanks

Goku

[Michael_NIUK]

Hi there, 

The SCTL executes all the code within it in one tick, you can find more information on it here;

Single Cycle Timed Loops

From your screenshot it looks like you have a for loop within the single cycle, could you replace the SCTL with a standard while loop and add some timing functions?

[GoKu25]

Hey,

I could try but the I2C Master VI that I use for interfacing dictates that I place it inside a SCTL  according to the documentation

thanks

[ha.nadine]

Hi Goku,

You could try writing the entire array at once to the FIFO by either allowing more elements for each write operation (in the FIFO Properties>>Interfaces category), or by specifying a Custom Control of Array type as the Data Type.

Regards,

Nadine

[Jacobson-ni]

If the FIFO isn't target scoped you won't be able to use a custom control but allowing more elements per write or using join numbers to bit pack all elements will probably work.

As a note for the future, you will run into another compile error because you are feeding a non-zero timeout into your FIFO write (you will need to change the interface to handshaking). The reason having a timeout isn't possible is because you are telling the FIFO that it might have to wait up to 5000ms before timing out but also saying that it needs to execute in one tick (because it is in a SCTL) these two conflict with eachother.

Also, do we have the return of Queen Nadine above me?

[ha.nadine]

You know it!

Nothing gets past you, Matt!

[GoKu25]

Hi Matt, 

Thanks for the reply. The FIFO is target to Host so I cant use custom control. So I'll try writing more elements into the FIFO.

I have one more question. Do you happen to know how the NI I2C IP package works for implementing I2C interface in FPGA. I am not sure if I'm doing the sensor initialization and write-read part the right way. Let me know if  aou are familiar or if you  could help me with that

Thanks a ton

Goku

[Jacobson-ni]

What problems in particular are you running into? I have used it in a project but have very little experience personally (someone else was in charge of making a simple API that I could use).

[GoKu25]

I am using the I2C master VI in the FPGA VI. I initialize the sensor and perform the write-read operation from the RT VI. When I write the initialization byte sequence, I don't know what the read out terminal of Master Vi is.

The documentation says:

The Read Data output returns the data serialized into the master from the data line of the I2C bus. Read Data remains valid until the next transaction is started after asserting “Go”.

I dont really understand what this means.