Labview RT - IRQ driven Data Streaming application problem

[yuval_yohai]

Hello,

I need to implement a cRIO application that will stream data to File or TCP/IP.

My data is 16 channels of 24bit analog signals sampled in 51.2KS/sec which need to be streamed through TCP/IP or into Files.

The architecture I was asked to implement is an IRQ based application.

I need to make the FPGA raise an IRQ each time the FIFO has reached half of its size, while the RT layer will have a multi threaded VI. One thread is a high priority "IRQ listener". Each time the IRQ is raised the FIFO is read, the data is then transferred to an intermediate buffer, and the thread is waiting for the next IRQ. The second thread is doing the TCP/File streaming or any other task.

Such an application requires a large FIFO DMA, much larger then the available size during FPGA compilation. For that I resize the FIFO from the RT layer.

My problems are:

1. Is this architecture a valid way to implement a streaming application? and what are the dis/advanteges?

2. I need the FPGA to sample the FIFO available size so that it will be able to rais the IRQ. I use the "Get Number Of Elements to Write" method from within the FPGA. This method returns a wrong value of which its maximum is the COMPILED size and not the RESIZED size of the FIFO. Why is that? it seems like a bug to me. And if it's not, then what would be the correct way to implement such an FPGA architecture.

Thanks,

Regards,

Yuval Yohai

[Fred_V]

Hi Yuval,

By resizing the the FIFO from Real-Time layer, we're essentially adding a temporary buffer that extends the FIFO. However, this is only happening on the Real-Time side; the communication is only one way between the FPGA and the controller. You might say that the FPGA is only locally aware. 

Is there a reason that you aren't just using a DMA Buffered Acquisition architecture (Example Finder » Toolkits and Modules » FPGA » FPGA Fundamentals » DMA » DMA Buffered Acquisition)?

The DMA FIFO.Read reports the Elements remaining, so you can monitor that value and choose to read when the buffer is 50% as required.

I hope this helps,

[yuval_yohai]

Hello Fred,

Thanks very much for your reply.

I understand that the FIFO is being resized at the RT layer, yet, to my humble opinion, the method should have been able to know about it otherwise it is useless.

My client ensists on me using this certain architecture. Does it has any disatvanges comparing to DMA buffered acq. architecture?

Obviouly, now that I read your answer, the IRQ architecture I am suggesting can not be implemented. Can you think of any other similar solution to implement such a concept?

Regards,

Yuval

[Fred_V]

Hi Yuval,

The IRQ architecture that you describes has additional overhead compared to DMA Buffered Acquisition's. Given that you need to pass the current FIFO size back to the FPGA, you would need to add additional code.

The standard architecture - used even in DAQmx - is the DMA Buffered Acquisition, and it should perform admirably for your application.

I understand that you have an existing issue open with a branch, so I'll let them continue to help from here.

Kind regards,