Matrix Multiplication in LabVIEW FPGA space

[Muri777]

Hey guys, 

Quite new to LabVIEW and FPGA architecture. I am trying to create a 4x4 matrix multiplication in the FPGA space (that is, have a 4x4 input matrix A and multiply it by 4x4 input matrix B and give a resulting 4x4 matrix as C). I have completed a few of the courses (labview 1,2,3, realtime 1,2 and fpga) but I am having a little difficulty with desigining something that will work in the FPGA space.

I have made something which fundamentally works but not in matrix form. It works with single inputs rather than inputting a matrix (see attached images) where it does each calculation seperately and pretends to be in an array rather than single elements.

Please help!

Any help would be incredibly appreciated. I have searched the web over the last week to no avail. Thanks!

[nathand]

LabVIEW FPGA cannot handle arrays with more than 1 dimension, so you'll need to come up with another approach. First, you'll need some code on the host system to convert from a 2-D array to a 1-D array that the FPGA can use. Then you'll need to decide how to store that 1D array on the FPGA. If it's a small matrix, a 1-D array as a control is fine; for a larger matrix, I'd consider using a memory block. If you have 2 4x4 matrices, I would make them 16-element arrays, then do the operation exactly as you've shown it but store the result back into a 16-element array, and in the host code reshape that back to a 4x4 matrix.

[Muri777]

Ah yep I see what youre saying. Yeah because FPGA doesnt like anything more than 1D it was being a little difficult. Im still very new to this (~1 week so far) so I am still trying to get my head around everything. Is there a straight up function that can represent 2D arrays as 1D on the host? Or is there some designing that needs to be done.

Thanks so much for your reply!

[nathand]

On the host you can use Reshape Array. If you know the array size you can wire a constant to it. If you don't, it will be much more complicated on the FPGA side, but you can use Array Size wired to Multiply Array Elements to get the total number of elements in the multi-dimensional array and use that as the size for Reshape Array.

EDIT: Also note that you can use Reshape Array to go the other direction as well, from a 1-D array back to a multi-dimensional array.

[Muri777]

Okay thanks heaps for your feedback - Ill give it a crack in the next hour and post how I go. No doubt I will still have issues haha.

Thanks again, will report back to this soon!

[LocalDSP]

Another question is what type of speed performances you want to achieve. If it's relatively low speed (up to a few MHz) you can serialize parts of, if not all your operations, but if you want to run your matrix operations at 100 MHz you'll have to parallelize all your operations.

That decision may also affect the way you are exchanging data between your host and the FPGA.

[Muri777]

Ulitimately I want it to run as fast as possible so will need to be running in parallel.

In terms of what I have done so far - Ive managed to get a 2D input being changed to a 1D array (on the RT side) but when its sent to the FPGA side I have no idea how to split it up into data into, say, the first 4 elements being the first row of matrix A etc. Does anyone have any idea how this is possible?

Thanks!

Muri

[nathand]

Can you be more specific about what you're trying to achieve? For example, are you always dealing with 4x4 matrices, or you need to be able to handle variable sizes?

If you're always doing 4x4, then on the FPGA you have a 16-element array and you can simply index out the elements: indices 0-3 are the first row (or column, depending on how you structured it), indices 4-7 are the next row, etc. The LabVIEW function is Index Array. You only need one of them, expand it down to index out more elements. If you don't wire in the index, then it defaults to indexing out the element after the one above it, with the first one being 0.

[Muri777]

My goal is to get two matrices that will always be 4x4 as inputs, send the data to the fpga to calculate the multiplication of the two matrices and send the result back to the rt.

Oh I kind of see what you mean - do you mean like this? So the first one will do elements 0-3, next will do 4-7 etc?

 
EDIT: so the output line up the top is a 1d array that i send to the FPGA. (this diagram is on the host side) would it be better to seperate them and send them as 4 seperate strings to the FPGA or send the entire 1D output to the FPGA and seperate them there?

[LocalDSP]

The keyword here is "RT''. Sounds like you have relatively low speed requirements. Can you tell us a little more about your system (cRIO?) and actual speed requirements?

Whether you serialize or parallelize your operations you obviously need to synchronize your communication with the host so there is no doubt when matrix element X(3, 2) is transfered. The requirement 'as fast as possbile' make it sound like a Host-Target FIFO transfer is the way to go.

Then as mentioned by nathand if you don't have a fixed 4x4 configuration, you should send that MxN information separately to your FPGA beforehands so it knows how to interprete the streaming FIFO data.