NI FPGA: ODD Timing Analysis Results/Bug

[Colonel1013]

Hello all,

LabVIEW 2014 SP1

LabVIEW FPGA 2014

Xilinx Vivado

I am getting some very odd timing errors when I compile my FPGA Bitfiles.

I do everything possible to ensure my critical path delays are minimized...and I believe the compile should be good.

However, I get compile failures that don't make sense to me.

See below.

My total delay is less than the requirement, yet it says it failed!

Am I reading this wrong?

[Colonel1013]

Another datapoint.

[Intaris]

If you click on the non-diagram component part, it should give you some information on where the problem is occurring.

Passing this information on to NI (along with the model of card you are using) would be useful.

Do you have any custom timing constraints regarding IO timing (BEFORE or AFTER timings)?  This can lead to timing violations due to clock skew even though the max. frequency might be achieved.  If you look at your compile log and search for setup & hold errors, this could explain what you are seeing.  Long-shot but I've seen something similar in the past(in the last two weeks actually).