LabVIEW
Need help with IP Intergration node on FPGA
Hi All,
Hope you are doing well,
I wish to integrate an IP Core that was provided to me in VHDL file format to LabVIEW FPGA. I can correctly setup the IP Block up until the clock setup page and if I select no clock, then it proceeds normally. Although, I need it to run on a derived clock 100Mhz so it must take clock input of my SCTL, 100Mhz.
Last night when I was setting it up, I was getting message stating that the clock enable pin is missing. I also came across some posts that talked about something similar. However, I can not come up with a way to apply the same in my case. This IP that I need to integrate, I am calling "Fancy_IP_Core", has 3 components in it that require a clock input. To simplify this, I have later created a top level VHDL code that is applying a single clock of 100Mhz to all 3 inputs. This clock in VHDL is generated by a clocking wizard using VIVADO 2022 tool. It completes all runs in VIVADO and generates a bitfile but I am not sure how I can transfer this VHDL code to LabVIEW. I know LabVIEW requires VHDL files from older VIVADO versions my only concern is with clock wizard related file as rest is basic code.
This morning when I tried again, either I missed a step or I changed something but I am not getting a clear message about clock enable pin, maybe I remembered incorrectly. But below is the current message:
"One port maps to more than one type of clock signal. The clock signal, derived clock signal, and enable signal must each be mapped to different ports in the IP." Please note that in this window, I am only using "Fancy_IP_Core" files without my top level VHDL code. This is to avoid any errors at my end.
Below is my proposed VHDL code (redacted), its main purpose, as far as this post is concerned is to have one Clock applied to all 3 internal components. VHDL below has some errors due to it being redacted, it is just to get the point across. Unfortunately, I do not have permission to share the IP Core but I ready to answer any questions.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.FANCY_IP_CORE.all;
entity TOP_LEVEL_Code is ----If needed, I would like to make changes to this top level file to make it LabVIEW compatible and leave rest the same.
Port(
clk_Pin_P : in std_logic; --On-board clock IOs
clk_Pin_N : in std_logic; --On-board clock IOs
e_rst : in std_logic; --IO to reset components
e_dsl_out : out std_logic; --- Uart_Txd
e_dsl_in : in std_logic; --- Uart_Rxd
e_dsl_en : out std_logic; --- Uart_TxEna
-- SPI 2 IO Reuse
e_spi1_miso : out std_logic; ---Srv_Ack
e_spi1_mosi : in std_logic; ---REQ
e_spi1_clk : in std_logic; ---Srv_Wen
e_spi1_ss : in std_logic); ---SR_SF
end TOP_LEVEL_Code;
architecture Behavioral of TOP_LEVEL_Code is
----------------------------Signals----------------------------
signal S_GEN_CLK : std_logic := '0';
signal SV_WEN : std_logic := '0';
signal SY_WEN : std_logic := '0';
signal DE_A_dummy : std_logic := '0';
signal RD_dummy : std_logic := '0';
signal s_locked : std_logic := '0';
signal st_buff : std_logic := '0';
signal s_WEN : std_logic := '0';
signal s_REQ : std_logic := '0';
signal status_M : std_logic_vector(2 downto 0);
signal RD_Buff : std_logic_vector(7 downto 0);
signal WR_Buff : std_logic_vector(7 downto 0);
signal Addr_Buff : std_logic_vector(7 downto 0);
signal SF_RD_Buff : std_logic_vector(7 downto 0);
signal SF_WR_Buff : std_logic_vector(7 downto 0);
signal SF_Addr_Buff: std_logic_vector(7 downto 0);
signal WR_in : std_logic_vector(7 downto 0);
signal Addr_in : std_logic_vector(7 downto 0);
signal Version_d : std_logic_vector(31 downto 0);
--------------------Component Declaration-----------------------
component All_CLK -----This is Generated Using VIVADO's Clocking Wizard (VIVADO 2022)
port
(
clk_out1 : out std_logic;
locked : out std_logic;
clk_in1_p : in std_logic;
clk_in1_n : in std_logic
);
end component;
component Data_Router is ----Route Data Buffer to channels
Port (
CLK : in std_logic;
SR_SF : in std_logic;
M_WEN : in std_logic;
WR_in : in std_logic_vector(7 downto 0);
Addr_in : in std_logic_vector(7 downto 0);
SV_WEN : out std_logic;
SY_WEN : out std_logic;
WR_Buff : out std_logic_vector(7 downto 0);
Addr_Buff : out std_logic_vector(7 downto 0);
SF_WR_Buff : out std_logic_vector(7 downto 0);
SF_Addr_Buff : out std_logic_vector(7 downto 0)
);
end component;
component Pulse_GEN is
Port (
CLK : in STD_LOGIC;
TRIG : in STD_LOGIC;
PULSE : out STD_LOGIC
);
end component Pulse_GEN;
component FANCY_IP_CORE is
port (
Srv_Clk : in std_logic;
Srv_Rst : in std_logic;
Srv_Rdy : out std_logic;
Srv_Req : in std_logic;
Srv_Ack : out std_logic;
Srv_Addr : in std_logic_vector(7 downto 0);
Srv_WrData : in std_logic_vector(7 downto 0);
Srv_Wen : in std_logic;
Srv_RdData : out std_logic_vector(7 downto 0);
Sfy_Clk : in std_logic;
Sfy_Rst : in std_logic;
Sfy_Rdy : out std_logic;
Sfy_Addr : in std_logic_vector(7 downto 0);
Sfy_WrData : in std_logic_vector(7 downto 0);
Sfy_Wen : in std_logic;
Sfy_RdData : out std_logic_vector(7 downto 0);
Uart_Clk : in std_logic;
Uart_Rst : in std_logic;
Uart_Rxd : in std_logic;
Uart_Txd : out std_logic;
Uart_TxEna : out std_logic;
Version : out std_logic_vector(31 downto 0)
);
end component FANCY_IP_CORE;
begin
--------------------Component Instantiation---------------------
Generic_CLK : All_CLK
port map (
clk_out1 => S_GEN_CLK, --output clock for anything that requries clk input
locked => s_locked,
clk_in1_p => clk_Pin_P --clk pins on FPGA board
clk_in1_n => clk_Pin_N --clk pins on FPGA board
);
WEN_PULSE : Pulse_GEN
port map (
CLK => S_GEN_CLK,
TRIG => e_spi1_clk,
PULSE => s_WEN
);
REQ_PULSE : Pulse_GEN
port map (
CLK => S_GEN_CLK,
TRIG => e_spi1_mosi,
PULSE => s_REQ
);
Router : Data_Router ----Route Data Buffer to channels
port map(
CLK => S_GEN_CLK,
SR_SF => e_spi1_ss,
M_WEN => s_WEN,
WR_in => Addr_in,
Addr_in => WR_in,
SV_WEN => SV_WEN,
SY_WEN => SY_WEN,
WR_Buff => WR_Buff,
Addr_Buff => Addr_Buff,
SF_WR_Buff => SF_WR_Buff,
SF_Addr_Buff => SF_Addr_Buff
);
FancyIP : FANCY_IP_CORE
port map (
Srv_Rst => e_rst,
Srv_Rdy => status_M(0),
Sfy_Rst => e_rst,
Sfy_Rdy => status_M(1),
Uart_Rst => e_rst,
Srv_Clk => S_GEN_CLK,
Sfy_Clk => S_GEN_CLK,
Uart_Clk => S_GEN_CLK,
Srv_Req => s_REQ,
Srv_Ack => e_spi1_miso,
Srv_Addr => Addr_Buff,
Srv_WrData => WR_Buff,
Srv_Wen => SV_WEN,
Srv_RdData => RD_Buff,
Sfy_Addr => SF_Addr_Buff,
Sfy_WrData => SF_WR_Buff,
Sfy_Wen => SY_WEN,
Sfy_RdData => SF_RD_Buff,
Uart_Rxd => e_dsl_in,
Uart_Txd => e_dsl_out,
Uart_TxEna => e_dsl_en,
Version => Version_d
);
end Behavioral;
--N
Adding information, I found the same message again and upon careful reading I have another question, do I even need clock enable pin?
The clock pins SRV_Clk, Sfy_Clk and Uart_Clk in the IP does need 100Mhz clock signal. How can I provide it?
Message below:
Okay, I implemented the concept I talked about and named a single clock pin CLK_in. Selected this as a clock input pin and it appears that LabVIEW is now sending clock pulses to it. Which then routes it to rest of the logic.
I know have two more questions:
1) Does this approach sound correct to you?
2) I now have a tiny caution sign on the IP block, it is safe to ignore it and how can I see that it is cautioning me about? Is the basically pointing to the warning in the IP Integration node properties window?
@Xonmyth wrote:
Okay, I implemented the concept I talked about and named a single clock pin CLK_in. Selected this as a clock input pin and it appears that LabVIEW is now sending clock pulses to it. Which then routes it to rest of the logic.
I know have two more questions:
1) Does this approach sound correct to you?2) I now have a tiny caution sign on the IP block, it is safe to ignore it and how can I see that it is cautioning me about? Is the basically pointing to the warning in the IP Integration node properties window?
This thing worked!!!! In my case this is the solution but I would not want to mark it so. I feel weird marking my own post as solution. Terry, I appreciate your suggestion, if the logic did not require a clock input pin your suggestion would be the solution.
