Need help with dma fifo in fpga, sensor initialization and some more stuff

[GoKu25]

Hi Folks,

The scenario is, I have a sbRIO 9651 and a MPU 6050 (A IMU sensor). I would like to acquire sensor data in FPGA VI, stream it to RT VI for processing and analysis and view it from windows based VI. I came across certain problems which I wasn't able to figure out. I dont have the appropriate cable to interface the sensor yet, which I have ordered, to test the VI.

1. FPGA VI:  The I2C Master VI outputs a array of 14 bytes raw data (6 bytes for Accelerometer, 6 bytes for gyroscope and 2 bytes for temperature). since the data can only be written element by element in a DMA FIFO, how can I stream an array to RT VI. I did an auto-indexed for loop to write data and I dont know if this will work.

2. RT VI: Initialization of MPU6050 is done here. It involves writing a byte array sequence to I2C Master VI to configure it and then a write-read(writing a register to read data from) process to acquire data. I am not sure how to do the write- read part.

3.  The single process shared variable 'RT Stop' used for communication between loops in RT VI is written a value after the loop ends which I dont know as to why. The architecture is based on the Turbine example from cRIO developers guide.

I am attaching the VIs for your reference. Please have a look into the code and let me know if you find anything that needs correction. I am totally new to Real time and FPGA programming.

Thanks a ton

Gokul

[NikoNR]

Hi GoKU25,

regarding your first question: I see two methods: either you add all output values bitwise, write it to the DMA and split it bitwise again. Or you simply use 3 of the 16 DMA channels that you have and write each value into a seperate DMA channel.

Just a quick thought on my site regarding the first question...

Best, Niko

[GoKu25]

Hi Niko,

Thanks for the pointer

Compilation of my FPGA VI on a sbRIO 9651 SOM resulted in a error

code: -61003

Possible reason(s):

LabVIEW FPGA: You cannot include this function in a For Loop when the For Loop is inside a single-cycle Timed Loop

From this I understand that I can't use for loop inside a SCTL. But I have to send a arrays via DMA FIFO. Is there any solution for this. I am attaching a screen shot of the VI

Thanks

Goku

[NikoNR]

Hi Goku25,

I actually thought to implement 3 DMAs for he Gyroscope and 3 for the Accelerometer. Does that work?

[GoKu25]

I don't have the hardware at the moment. I'll get it back on tuesday and i'll let you know if it works. I have other sensors to interface as well. so using 3 fifo for each component at the moment will take up 7 fifos and more resources

[NikoNR]

ok, let me know, if it works!

[GoKu25]

Sure, I have a question to ask. On the FPGA VI, I try to acquire data from a senor in SCTL at 40 MHz. Now Im writing an array of 3 elements to each of the Acc and gyro FIFOs. The FIFOs are configured to have

Requested num of elements: 20,000 

Data type:I16

Number of elements per write is 4

On the RT VI

I've configured the depth of FIFO as 100,000

Im reading the data in Timed loop configured at 1MHz and loop period of 30microsec

Num of Elements to read: 3

Time out: -1

And then I'm using the index array function to get the individual elements.

What could be the optimal size of the FIFO and the properties for the communication process?

Thanks

Goku