Number of elements in target to host DMA FIFO

[markus_a]

Hi everyone,

I'd like to transfer a set of datapoints from a FPGA to a RT-host controller using a DMA fifo. If I use the "Get Number of Elements to Write" function on the FPGA target, do I get the total number of elements in both buffers, or just the one on the FPGA-target?

(see http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_dma_how_it_works/)

[christian_w]

- create the DMA FIFO under the target in the project explorer

- set its properties (number of elements)

The host sided buffer is by default 10000 elements or twice as big as the target (FPGA) but this can be overwritten.

Read the LabView help --> FIFO.Configure (Invoke Method) or this thread FIFO depth

- the host side write method returns the 'empty elements remaining'

- the target side status method returns the 'number of elements to write' (from LV help: "The number of elements that this method returns is less than or equal to the actual number of elements available to write to in the FIFO.")

Hope it helps

Christian

[crossrulz · Accepted solution]

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markus_a wrote:

If I use the "Get Number of Elements to Write" function on the FPGA target, do I get the total number of elements in both buffers, or just the one on the FPGA-target?

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The FPGA will have no clue how big the DMA is on the host side.  It can only see its own DMA buffer.

The Get Number Of Elements To Write just tells you how many elements are not being used by the DMA (ie number of elements you can currently write to the DMA without waiting for elements to be opened up by the host reading).

[markus_a]

Thank you. I was affraid it works that way

[GregSands]

That should be a relief, not a problem!  All the FPGA needs to care about is its own buffer not filling up.  It's usually straight-forward to make the host buffer as large as you need, or to create a small loop which just pulls data off the DMA onto a local Queue.  The only issue could be if the FPGA-Host transfer can't keep up with the data rate, but in that case (which I'm not sure will happen anyway), knowing the size of either buffer is not going to help a lot.

[markus_a]

I normally agree with you, but I wanted to use the function for another problem:

I want to transfer two signals (one triggered on the rising- and the other on the falling edge) from the FPGA to the host system. The host takes both signals and makes some calculations. Since the time of the calculation is not deterministic and depends on certain parameters,  I want to limit the number of signals in the FIFO to one (one pair of signals). So my idea was to check the total number of samples in the FIFO to determine if the FPGA can start measuring a new signal. I also tried setting the size of the host FIFO to the actual number of samples in one dataset, but I can’t set it that small. My second try was to use a read/write counter. This works for some time, but if the systems fall out of synch (for example because one trigger was missed), it stays that way.

Does anybody have an idea how to implement this problem?

[MrQuestion]

What type of data do you want to transfer over the FIFO? As in how many bits does each sample contain.

The reason I ask is because you can take a bit packing approach.

Lets take for example you want to take two samples of a measerment both samples are 32 bit and then send the data as a set to the processor.

If you just dump the data into a single FIFO you may lose track as to what was the rising edge, or falling edge data, or if the two samples you got from the FIFO are even from the same dataset.

To fix this use bit packing technique.

On the FPGA merge your two 32 bit data sets into one 64bit dataset. 

Set your FIFO to 64 bits.

On the processor side of things all you need to do is read one 64bit dataset from the FIFO.

Use the split data to break the 64bit into two 32bit data fields. 

Now you have your two data samples, and you can be garentee that it is from the same dataset.

If the sum of the data bits exceed 64 bits (the limit of the FPGA FIFO) then you will need to migrate to a more complex bit packing data schema where the data is split up among multiple 64bit datafields, with a defined bitfield header and identifier. For example the first 5 bits of the 64bit data identifies that this data block is 1 out of X data blocks, that when combinded together and reasembeled per the schema will represent your data..

I hope this helps.

[GregSands]

If I understand correctly, you want the FPGA to know when the host has finished computing so it can acquire and send a new pair of signals.  Can the host just set a Boolean when it's done? 

If the FPGA misses a trigger, presumably it knows that, i.e. it gets two rising or two falling signals in a row.  Can it send a "null" signal to signify to the host that it should discard the previous data, and send the new information?

I'm feeling like I'm missing the point, so hopefully these spark some ideas that do what you actually need!

[markus_a]

Thank you for your input.

I'm allready using a bit packing approach combining four 16bit integer to a U64. But since I don't need one of the four channels anymore, I can use this one to add some information. 

I don't want to set a boolean variable to speed up the system. The idea is to transfer the next dataset while the host is still calculating. By doing so I hope to increase the utilization of the host.

[christian_w]

Can't see a meaningful use of a FIFO in this szenario. If you want to limit the FIFO input to just a pair of data it's probably better to use control communication with a handshake.

The speed of your app is determined by the host calc time so the FPGA is just waiting.

You should check if the calc can be done by the FPGA. Send your params down to the FPGA and you'll have a really fast application.