Optimize increment or decrement operator for FPGA

[Mariano76]

Hi all, i'm wondering if there is a solution to optimize the increment +1 or decrement -1 operators for execution speed having as target increasing the SCTL clock speed.

I mean substitute those operators in the same fashion as the equal to zero is optimized converting a number to a boolean array and after that checking bit to bit and putting an AND or OR operator (attached pic)

[Dragis]

Are you running into issues becaue the integer data type you are using is much larger that what is required? If you use compact fixed-point types instead of integers you will most likely not be able to implement anything faster than what the compiler generates for those operators. For instance, if you only need a 4-bit values, use a fixed-point type configured to that and then use the standard primitives. No bit-twiddling required, the compiler will do it for you.