PXIe-7820r, Octoclock External clock 10MHz Synchronization

[Michol]

Hello,

I am a beginner with LabVIEW! Currently, we are using the PXIe-7820R module.

We have written our FPGA code using the on-board 40MHz clock, but now we want to synchronize it with a 10MHz external clock generator (OctoClock).

Therefore, we intend to connect the 10MHz OUT from the OctoClock to the 'CLK OUT' of the SCB-68 HSDIO terminal block and check if other output terminals are synchronized with the signal coming from the OctoClock.

When we refer to the FPGA code above and compile it, we encounter the following error:

1. Could it be that the OctoClock is not properly connected?
2. Is it correct to use the above FPGA code to receive and synchronize the external clock from the OctoClock?
3. When the OctoClock is connected to the CLK OUT part of the terminal block, will the external clock's time loop in External Clock 0 automatically output according to the 10MHz signal from the OctoClock?

Thank you.

[ZYOng]

Most of the FlexRIO modules have external clock line inputs that can be exported to a Single-Cycle Timed Loop (SCTL). As for the R-Series and CompactRIO product lines, there is no direct way to export a digital input line directly to an SCTL. You can either derive a new clock from the base clock of the FPGA or, if using a PXI system, export the 10 MHz backplane clock to an SCTL. 

One workaround that can be implemented is to have one SCTL reading a digital line, and another SCTL monitoring a local variable from the previous loop and checking for edges. I have attached a screenshot displaying a certain portion of code executing when the digital input has a rising edge (false to a true). This implementation will not have the accuracy of a directly exported clock; however, as long as you are using the default 40 MHz timebase for the timed loops reasonable frequency for the digital input, I don't believe you should miss any edges. 

Reference: Re: Timed Loops with External Clocks 

[Michol]

Thanks for the reply. 

I'm kind of confused, do you mean I can't synchronize directly with the exported clock(octoclock 10Mhz) when using PXIe-7820r? 

THANK YOU! 

[ZYOng]

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@Michol wrote:

Thanks for the reply. 

I'm kind of confused, do you mean I can't synchronize directly with the exported clock(octoclock 10Mhz) when using PXIe-7820r? 

THANK YOU! 

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You cannot route the external 10MHz clock to PXIe-7820R directly.

I just realized that there are shipping examples to route an external clock to SCTL. If you are using <LabVIEW>\examples\R Series\Device Specific\PXIe DIO Devices\External Clock\, try the steps in  Error -61046 Using When Compiling FPGA Code That Uses External Clock

You can try <LabVIEW>\examples\R Series\FPGA Fundamentals\Timing\External Signal for Loop Timing as well.

Alternatively, you can connect that 10MHz clock to the PXIe CLK_IN port, then Synchronizing the R Series or FlexRIO FPGA Clocks to the PXI Backplane. Note that not all NI PXIe chassis has the CLK_IN port.