PXIe-7975 DRAM question

[vekijag]

Hi All,

I am trying to achieve maximum DRAM throughput on PXIe-7975.
I read this article:

https://www.ni.com/en/support/documentation/supplemental/21/three-steps-to-using-dram-effectively.ht...

but I could not find information about DRAM organization.

Currently 25 bit address is used for addressing 512bit data location.

2^25*512 = 17179869184 bit = 2GB

This 25 bit address consists of bank, row and column address. Does anyone
know how many bits form each of these adress? I used DRAM on PXIe-5644R
and could configure DRAM as socketed CLIP and all of this information was provided.
Why Labview does not allow configuring DRAM as socketed clip on PXIe-7975 platform?

Thank you in advance.

[jozef.liptak]

Dear vekijag,

the info (row/column addresses, basically memory organization) was provided on 5644 because it was possible to configure DRAM as socketed CLIP. To achieve max. throughput on 7975 it is enough to follow the info on the by you mentioned tutorial (use datatype that has 512bit width and push the data to the DRAM with optimal clock rate). 

Long story short, users can't use socketed CLIP to interface with DRAM on our Kintex-7 FPGA (7975 uses Kintex-7 XC7K410T) modules because our RnD observed that in most cases, socketed CLIP does not offer significant benefit over the LabVIEW memory item implementation, and thus chose not to do the extra work to support it.

B/R

[vekijag]

Hi Jozef,

Thank you for your reply. I still think that information about row and column address is important in order to achieve best performance. Opening a row in a bank for access spends time which decreases throughput. My system requires reading and writing data to DDR3 at the same time. For example if the row address width is 15 bits and column address is 8 bits I will get the best throughput if I write 256 samples to some location and than read from some other location 256 samples and so on. To achieve this I need to put block RAM based FIFOs before and after DDR3. For some other widths FIFO should have other size.

Best Regards,

Aleksandar  

[jozef.liptak]

Aleksandar,

now I am not really sure if I understand how you want to access the Memory Item in your project under the 7975 target (implemented as DRAM). Personally I think, it is not necessary to use FIFOs manually created in the project (implemented as Block Memory / BRAM), because then you need to handle them (and maybe unnecessary think too low level).

You can use DRAM FIFO from the FlexRIO FPGA Libraries palette (Create, Read, Writte). Please take a look into the example finder, where you can find "Memory Throughput Test (FPGA).vi"(snipped attached) that uses those FIFOs to access DRAM and you can test the throughput with given parameters (even with different data - just some modifications needed).

To what throughput  values are you aiming? Maybe it is not even needed to be concerned and it will work fine as it is within your application - just keep to the full DRAM data width (512b in this case) and push the data to the DRAM with the optimal speed.

 

B/R 

[vekijag]

Jozef,

I am actually using PXIe-7976R and PXIe-1085 24 GB/s chasis. I am receiving data from PXI express at maximum speed of 3.2 GB/s and writing
them into DDR3 memory implemented as circular buffer. I am processing data and if some conditions are met I need to start
reading from DDR3 memory at speed of 3.2 GB/s. I can not stop writing. So I have overall rate of 6.4 GB/s and that is the reason I have to think
low level. Maximum theoretical data rate is 10.5 GB/s according to https://www.ni.com/docs/en-US/bundle/pxie-7976-specs/page/specs.html. So DDR3 operates at 1333 MHz. Theoretical data rate can be achieved only if write or read can be done on every clock cycle which is not possible because of following overheads:

-precharge time accessing rows in the same bank (Access address not in the same row-page hit) 

-write recovery time to change from write to read access

-bus turnaround time to change from read to write access

-ZQ calibration

etc...

For programming I am using HDL languages and inserting clip node. FIFOs which I mentioned are implemented inside clip node. 

Part Number of DDR memory would resolve all my questions...

Best Regards,

Aleksandar

[jozef.liptak]

Dear Aleksandar,

makes more sense. Still, why did you start with 7975 question if you are working with 7976? Most probably the DRAM will be organized the same, but still. Thanks for the clarification. In the light of the current info I did a little research at our side and it is hard to find those information's. But it is possible and I found some things that could be helpful for you. Still: it seems that the memory organization has most probably changed in time, definitely the memory addresses mapping change was planned to be more efficient. To get to the current info, that are important to you (in regards to your HW revision and SW that you use) I suggest you to contact your local NI technical support (as this question will need to be escalated to RnD), or simply create a ticket in Service Request Manager in your ni.com profile. I am certain this will be more efficient and targeted towards your needs.

Have a nice weekend!

[vekijag · Accepted solution]

Jozef,

I started doing my project with PXIe-7975R but it can support streaming data at 1.5 GB/s over PXI express(PCIe Gen 2x4). The PXIe-7976 uses a PCIe Gen 2x8 interface, allowing it to stream up to 3.2 GB/s. Today I found answer on question by looking at PumaK7Top.xdc file provided by NI during compilation. 

Bank width 3 bits

Row width 15 bits

Column width 7 bits

[David-A]

The DRAM FIFO can already hit the rates you mentioned with plenty of room to spare on the 7976. Try running the following example from the example finder, Hardware Input and Output>>FlexRIO>>External Memory>>Memory Throughput Test. You'll see that you get a sustained throughput of about 9GB/s using the DRAM FIFO. You can dynamically shift that throughput to writes only or reads only or 50/50 reads/writes as you see fit.

More power to you if you're able to get the socketed CLIP working and it does what you need, but it seems like extra work you don't need to do since there is existing IP that meets your needs.