Problem with Conditional Disabled Structures in LVLIBPs

[Universaldilletant]

Hey community,

we have a problem with conditional disabled structures in LabVIEW 2023Q3 32bit on Windows:

Our workflow is the following:
- We develop code (usually DQMH modules, but it doesn't matter) in LabVIEW libraries and when the code is done, we build them into LVLIBP

- Our code often has a conditional disabled structure as flag which is called "HARDWARE_ENABLED" and we either set that to True or False on project level

- In the pre-build vi, we set the flag to True

- We move the built LVLIBP into a new project that utilizes this code. The new project has the same "HARDWARE_ENABLED" conditional symbol defined in the project
- we start the new project with the flag HARDWARE_ENABLED=True
- We open a VI with a Conditional Disabled Structure, but the code that is set to "Default" is still marked there, in this case "HARDWARE_ENABLED==False".
- We set the flag to "False" once at project level, save the project and set the flag to "True" again (in essence toggle the behaviour)
- It sudenly works

Do you have any idea why?

Steps we have already taken:

- searched the forum sites here and in LAVA

- checked for typos and capitalization errors since conditional disabled structures are case sensitive

- deleted the build cache before building the LVLIBP file

- Tried it on 3 different computers (2 PCs, one build server)

Thanks a lot for any hints!

Cheers,

Niko

[raphschru]

Hi,

The fact that your compiled VI still shows the Default case can mean that you are not setting the CD symbol (short for Conditional Disable Symbol) correctly in the Pre-Build of your PPL. Here is how I would do:

Then, the fact that changing a CD symbol in your second project can change the state of CD structures (short for Conditional Disable Structure) inside a compiled VI is really weird. To me this should not happen, as the active frame of any disable structure should be fixed at compilation (unlike case structures where the diagram to execute is determined at runtime).

After some testing, it seems to happen only if you include the block diagram in your PPL VIs. In some way LabVIEW can still change CD structure of compiled VIs if it has access to their block diagram. I don't think that's an expected feature, but more a bug, because it only happens after you change the CD symbol in your second project...

Attached are the projects to reproduce this weird behavior (bug?).

Steps:

1. Open project "Use PPL.lvproj"

2. Open VI "Test Use PPL.vi". This is just a wrapper for a PPL VI. Run it. It displays message "Hardware is enabled."

3. Edit project conditional disable symbol "HARDWARE_ENABLED" from "False" to Falsee". This is just to trigger the bug.

4. Run again the VI, it now displays message "Hardware is disabled."

Now do the following:

5.Close project "Use PPL.lvproj" and open project "Build PPL.lvproj"

6. Edit the build specification, go to Source File Settings, check "Remove block diagram" for "Lib VI.vi"

7. Build and close the project

8. Repeat steps 1 to 4, now the displayed message does not change anymore and stays "Hardware is enabled." as expected.

Regards,

Raphaël.

[Universaldilletant]

Hey Raphaël,

thanks for looking into this!

I don't have access to my Laptop, so I can't test this atm, but we are compiling with debugging enabled. I am wondering, if this might be another root cause.

Thinking about it: what is the difference in "Enable debugging" and "Remove Block Diagram" in a lvlibp?

That question is really out of curiosity.

Cheers,

Niko

[Universaldilletant]

On a second thought:

what is the expected behaviour for a LVLIBP with conditional disable structure?

Is it expected to remove all cases on compilation where the conditions are not met?

I think that would only make sense for the specific structures that target e.g. processor architecture.

Can anyone from NI jump in?

Cheers,

Niko

[raphschru]

I think "Enable debugging" is just a higher-level setting that forces including all diagrams whatever are the Source File Settings.

So in your case all diagrams are always included.