RIO FPGA to Host FIFO Jitter

[major4x]

I was wondering if somebody could advise. The design that causes my problem is attached. It is kind of an averaging oscilloscope (data is written to a binary file). The problem is that I get jitter every N samples like this:

The problem is related to the FIFO because the jitter appears every N samples and N = size of the host-side FIFO. I tried with host-side fifo of 4096, 512, 128 bytes and then I get jitter every 4096, 512, ... points. I thought the problem is related to arbitration and I set no-arbitration to all FIFO's and I think that the design works a little bit better but I still get the jitter and it could be wishful thinking that it is less jitter. So, I am really out of ideas what to try next.

[ThiCop]

Hello Major,

Is there a specific reason why you are aborting your FPGA in the beginning of your Host Code, instead of resetting it?

Can you try one test for me?

Can you check (at the host side) if there is still any data left in your FIFOs before you start the acquisition at the host side?

This would come down to trying to read out all data with a fixed timeout value.

For some reason I have a hunch feeling that this "jitter" might just be old data that was still in the FIFO.

[nathand]

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@ThiCop wrote:

For some reason I have a hunch feeling that this "jitter" might just be old data that was still in the FIFO.

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This was already solved - by the original user, posting under a different username. Unfortunately he chose to explain the solution in an insulting message to himself, which I suppose he thought was funny but wasn't appropriate for the forum and was likely deleted by a moderator. If I remember correctly the solution was related to using flatten to string with the "Prepend array or string length" input set to true, so every n elements there was one unusual value of the array length.

[ThiCop]

Hello Nathand,

Thanks for the feedback!

We had some issues in finding the right post back via the notification.

Probably this was linked to this deletion.