RT FIFO vs. single process shared variable with RT FIFO enabled

[julienp]

What is the difference / tradeoff between those 2 mechanisms to pass data between a high priority timed loop and other lower priority loops?

From a implementation point of view the shared variable is easier to use and makes the block diagram a little cleaner, but are there disadvantages to that approach?

In my specific application the FIFO should never really have more than 1 element, assuming the lower priority communication loop keeps up with the higher priority timed loop.

Thanks

J

[Jim_S]

Hello J,

Overall the RT FIFO and the shared variables with the RT FIFO enabled are generally the same thing. I will list the differences between the two below for your information.

RT FIFO Benefits:

1.) RT FIFO allows you to change the configuration dynamically in your program

2.) RT FIFO has less overhead than the shared variables which will allow faster write operations and will increase execution speed.

3.) Backwards compatible to LV 7.x

Things to think about when programming with RT FIFO:

1.) Make sure you set the memory allocation for the buffer so that it does grow without bound.

Shared Variable with RT FIFO enabled benefits:

1.) Shared Variable's configuration is set statically so your couldn't change it programmatically

2.) Contains timestamps when the writes occurred

3.) Easy to use and aviods using the lower level VIs

4.) Backwards compatible to LabVIEW 8.0

Disadvantages:

2.) Write operations to these variables are slower and use more memory because they must include timestamp.

I hope this information helps you with this and if you have anymore questions feel free to post them.

JimS

[julienp]

Great, that is exactly what I needed to know. Based on the information you provided, it seems that I should use RT FIFOS to minimize memory use and maximize write speeds.

Thanks,

J