Random Aliasing/Data Misread Using NI 5752B

[bisheramer]

Hello all,

I am using the NI 5752B ADC module along with the PXIe-7972R FlexRIO FPGA. The former just maps out the voltage of an incoming signal across 32 channels, and streams it from the FPGA to the Host PC through a DMA FIFO (First In First Out) memory buffer. I have noticed that at times, when I am reading in the the signal with LabVIEW, I get some sort of aliasing which seems to be in a somewhat regular sample range (for example, 1171).

I've attached a photo of how it looks. It seems to always be around 1171, or 2200-something. The code I am using is built upon LabVIEW Examples, also attached.

I have a feeling that it could be due to the FIFO not fully flushing, and having remnant samples. Am I missing something here? Could I be missing a "Reset DMA FIFO" function somewhere?

Any advice is duly appreciated.

 

[Terry_ALE]

Can you attached the LabVIEW project?

The examples are written to get bursts of data.  How are you ensuring that things remain continuous?