Timing violation in labview fpga

[FraBaggio1]

At the moment I've been performing some experiments about monitorizing the on-die temperature (inplementing the primitive SYSMON) of FPGA Virtex 5 using cRIO LABVIEW FPGA (with STCL of 40 MHz). As a heater core I decided to use a pipeline of Toggle T flip flops and also FF+LUTs. At 100 MHz (inserting a PLL to my VHDL design) I occupy almost all the Slices FF and LUTs resources of my FPGA: I designed two pipelines 20000 FFs and 20000 FF+LUTS. When I enable the heaters I observe (picture enclosed) a rise of maximum temperature 2º C in 10 minutes. Should not it be more? Unfortunately, the timing violations occur at higher frequencies. For instance at 200 MHz a timing error happens with 13000 FFs. What I want to observe is more significant changes in temperature and that's why I want to increase the clock frequency, but timing violations don't allow me to do that. Where am I wrong?

Thank you very much.

[FraBaggio1]

At the moment I've been performing some experiments about monitorizing the on-die temperature (inplementing the primitive SYSMON) of FPGA Virtex 5 using cRIO LABVIEW FPGA (with STCL of 40 MHz). As a heater core I decided to use a pipeline of Toggle T flip flops and also FF+LUTs. At 100 MHz (inserting a PLL to my VHDL design) I occupy almost all the Slices FF and LUTs resources of my FPGA: I designed two pipelines 20000 FFs and 20000 FF+LUTS. When I enable the heaters I observe (picture enclosed) a rise of maximum temperature 2º C in 10 minutes. Should not it be more? Unfortunately, the timing violations occur at higher frequencies. For instance at 200 MHz a timing error happens with 13000 FFs. What I want to observe is more significant changes in temperature and that's why I want to increase the clock frequency, but timing violations don't allow me to do that. Where am I wrong?

Thank you very much.

Kind regards,

Francesco 

[FraBaggio1]

At the moment I've been performing some experiments about monitorizing the on-die temperature (inplementing the primitive SYSMON) of FPGA Virtex 5 using cRIO LABVIEW FPGA (with STCL of 40 MHz). As a heater core I decided to use a pipeline of Toggle T flip flops and also FF+LUTs. At 100 MHz (inserting a PLL to my VHDL design) I occupy almost all the Slices FF and LUTs resources of my FPGA: I designed two pipelines 20000 FFs and 20000 FF+LUTS. When I enable the heaters I observe (picture enclosed) a rise of maximum temperature 2º C in 10 minutes. Should not it be more? Unfortunately, the timing violations occur at higher frequencies. For instance at 200 MHz a timing error happens with 13000 FFs. What I want to observe is more significant changes in temperature and that's why I want to increase the clock frequency, but timing violations don't allow me to do that. Where am I wrong?

Thank you very much.

Kind regards,

Francesco 

[FraBaggio1]

At the moment I've been performing some experiments about monitorizing the on-die temperature (inplementing the primitive SYSMON) of FPGA Virtex 5 using cRIO LABVIEW FPGA (with STCL of 40 MHz). As a heater core I decided to use a pipeline of Toggle T flip flops and also FF+LUTs. At 100 MHz (inserting a PLL to my VHDL design) I occupy almost all the Slices FF and LUTs resources of my FPGA: I designed two pipelines 20000 FFs and 20000 FF+LUTS. When I enable the heaters I observe (picture enclosed) a rise of maximum temperature 2º C in 10 minutes. Should not it be more? Unfortunately, the timing violations occur at higher frequencies. For instance at 200 MHz a timing error happens with 13000 FFs. What I want to observe is more significant changes in temperature and that's why I want to increase the clock frequency, but timing violations don't allow me to do that. Where am I wrong?

Thank you very much.

Kind regards,

Francesco 

[David22JRA]

Hello FraBaggio1

I would like to know what are you using to create the Flip-Flops? are you using LabVIEW FPGA Module?

On the other hand the Temperature variation is pretty slow so, It is not necessary to read the temperature in high freq.

Could you give more details of the application you are trying to create?

Regards