Running FPGA code in debug

[Jonzarwal]

Hi all,

I’m encountering the following problem with LabVIEW FPGA on cRIO.

1. I code my FPGA VI in a LabVIEW project on a cRIO 9039. Once completed, without any further action, I click the "Run" button on the VI. This automatically triggers a compilation and then runs the VI in debug mode. Perfect.

2. I modify my FPGA VI, but I don’t have the cRIO available at that moment. I still click "Run" to launch the recompilation of the bitfile, but when it’s time to execute, LabVIEW indicates that the target is not available. No problem, at least my bitfile is ready for next time. I close LabVIEW.

3. When I’m back with the cRIO, I open the project, click "Run", and LabVIEW asks me to compile again, even though I already did. I can even see my updated bitfile in Windows.

=> How can I make LabVIEW understand that the bitfile is already ready for debugging? The compilation takes nearly 50 minutes, so this issue is very frustrating.

[Intaris]

Running debug code in interactive mode is very tricky. It's great when it works, but it doesn't work a lot of the time.

If ANYTHING changes in the internals of the VI, the compiler will be conservative and require a new compile.

You CAN create a wrapper VI where you open an FPGA reference, use the read/write controls to create a faux-interactive VI which is then decoupled from the actual source code. You can then save your bitfile under a different name and re-run it whenever you want.

Even a single conditional disable buried 7 levels within your VIs will cause the recompilation to trigger. I had used the interactive mode a lot int he past, but I've switched to 100% creating faux-interactive VIs since a couple of years. Life is a lot less complicated now.

[Jonzarwal]

Thanks for the feedback. That's not a bad idea! just a little additionnal work to recreate a nice layout on the FP of the new VI. 
I would still be glad to understand a little more how the interactive mode works, as it's easier to call the VI directly than from a wrapper. I'll post here if I find anything useful.

[Intaris]

I don't mean calling the VI, I mean using "Open FPGA Reference" and then using this interface to read/write the FP controls in a loop.

The fact that you are NOT using the VI means that you can archive old bitfiles and have the ability to do testing across different versions long after the VI itself has changed.

[Intaris]

As an addition, this VI is then executed on your host PC. You will need connection to the hardware of course and the appropriate drivers on your PC (Which I'm assuming are already there if you're programming it).

I used to be a huge fan of interactive mode, but now I use almost exclusively this mode of debugging. Being able to mix in some host code for formatting / interpretation of data makes is just too useful to leave behind.