Shift Register Look-up Table (SRL) in LabVIEW FPGA

[nmbernardo]

Hello. Is it posisble to implement a Shift Register Look-up Table (SRL) in LabVIEW FPGA? If yes, how can I implement it?

[srm@viewpointusa.com]

two ways.

either use the xilinx tools to generate an IP core that implements a SRL and import it using a CLIP node or implement it yourself in LabVIEW FPGA.  if you do it in LabVIEW, you should consider implementing in VI scoped memory using circular buffer logic

[david1147]

Try "FPGA Math->High Throughput Math->Basic Elements->Discrete Delay". That node is mapped precisely to a SRL on FPGA chip.

[srm@viewpointusa.com]

Nice.  configure for dynamic.  Learn something new every day.