Simulations in FPGA

[scps]

Hi all,

I started learning LabVIEW FPGA very recently and I have a query regarding the simulations that can be done. I don't have any NI FPGA hardware with me. I am using only the development computer for programming in LabVIEW FPGA.

 I am using "Execute VI on»Development Computer with Simulated I/O"option when I add only FPGA in my project to simulate some simple codes. But when I try to add Real Time system and then add FPGA, I/O ports never get listed under FPGA. I am attaching a snapshot of Course Manual of LabVIEW FPGA and project file I tried to replicate from the same. You can see that there are no I/O ports listed in my project file. 

How to get these ports appear in my project file without posessing any Hardware? ( I have replicated the steps given to simulate CompactRIO or Single-Board RIO in http://digital.ni.com/public.nsf/allkb/F466AD83D24F041D8625714900709583 , but when I added a program and compiled it, it gave error after it couldn't find the real time target). 

If I am able to add the ports, is it possible for me to get the simulated waveforms from those ports like I can view waveforms using ModelSim? Is it not possible to create a complete project and check the input and output waveforms in simulator on the development computer itself without having any of the hardware?

Kindly help me out. Thanks in advance.

Sharath

[Dragis]

In the right-click menu for the FPGA Target you can find options to add additional I/O and modules.

[scps]

@ Dragis :

I didn't find any such option. In one of the hands on sessions I attendded, as soon as the FPGA Target is selected, all the I/O ports appear. In the software, it won't happen like that?What am I missing here?

Can you tell me about the simulation also? 

[T-REX$]

Hi Sharath,

The reason the hardware list isn't auto-populating like you expect is that the project has never been connected to actual hardware. When setting up the project with real hardware, it can auto-populate the project with the items in your target. For a simulated device (I can see your IP address is 0.0.0.0), there is no way of knowing what different targets or modules you will want to communicate with.

To add IO to your project, you will want to right-click your FPGA target (RIO 0), navigate to new >> C Series Modules... This should get you to the "Add Targets and Devices on FPGA" window. From here, you can re-scan real hardware, or add a new simulated device by selecting the New Target or Device radio button, and double clicking the C Series Module option. This will bring up a window where you can name and select any module you want to add to the project.

The project in your first picture shows a 9211, a 9233, and a 9263 in it, all of which can be added to a simulated target in the manner described above.

What would you like to know about simulation? I see that you have your target set to execute on the development computer with simulated IO. This will allow you to run and debug your FPGA VI's logic just like you would a LabVIEW host VI. All IO will be simulated with random values by default.

[scps]

Thanks T-REX$. That was helpful.

When I was talking about simulation, I wanted to know if I can see the simulated waveforms at input,output or various stages of programming in LabVIEW FPGA in the similar fashion we can see in ModelSim. I know that we can port the project into ModelSim itself. But it seemed like a tedious process. No other way out?

[T-REX$]

Well, what you're asking for is a very common request, and I definitely agree that being able to see waveforms from within LabVIEW would be extremely useful.

It is really straight-forward to use ModelSIM, as you mentioned, or even ISIM (ships with the LabVIEW FPGA Module Compilation Tools) to get simulated waveforms.

ISIM can get a little difficult if you need to simulate the host interface, as this requires VHDL knowledge to write a test-bench. Fortunately, there is a really easy way to work around needing to write VHDL to provide the diagram with data. My usual method is shown here:

Using a conditional disable structure like this lets you pre-load a memory block with IO data. You can even use an initialization VI to load in TDMS or CSV data if you want. (the default case just has my IO item)

If you do have access to ModelSIM PE, Cycle Accurate Co-Simulation is a really powerful tool, and I highly recommend it. It's probably less tedious than you think once you get used to it.

Cycle accurate simulation is currently only supported on some targets, and unfortunately not the 9074 that you appear to be using. For simulation, I would recommend adding an RSeries(784x or 785x) or FlexRIO device to the project to simulate small pieces of code.

[scps]

Thanks for the help  T-REX$ .