Sine wave generation FPGA

[Slev1n]

I have a short question regarding the "Sine wave generation" function on LabVIEW FPGA.

There is the option to output sine and cosine parallel.

Is the frequency resolution still: res = Fclk/2^B = 40MHz / 2^32 ?

Fclk=clock frequency

B = accumulator width

kind regards

[r_good]

You can covert the express VI to see how they output the cosine.

You will see the cosine is not interpolated if you choose to interpolate the sine but can easily be modified to do so.

[Slev1n]

Thanks for your answer. I have not many ressources left.

So interpolating is not an option.

But I still do not see, if the signals frequency resolution is still the same? I guess it is, as the accumulator width and clock frequency is indepent from the use of sine and cosine parallel. Can you confirm this or am I overseen some fact?

[Slev1n]

And if I would use interpolation for both, is this the correct modifying?

[r_good]

The cosine output is just a phase shifted sine output, so it shares the same clock (top level 40M) and accumulator width.

[r_good]

I would clean up the case structure a bit more (the outside looks good enough, I do not have any AO cards to try this on) to ensure that you have duplicated the code correctly 

I think you are finding yi for the cosine correctly, just clean up the fractional calculation and then fire it up.

Use another AI or an OSCOPE to see how they work.  If you have an AI card (assuming cRIO, I am unsure what your HW set up is) you can use the extract single tone on each singal to measure the freq and phase and look for any problems in the generation.

[JLewis]

Unfortunately, modifying that VI will only work for desktop simulation; the actual hardware execution code is written in VHDL. That's what the comment above the While Loop is trying to convey.

If you want to do your own custom G implementation, this code shows the basic algorithm, but you would have to get rid of the floating-point types, and place the code in its own single-cycle timed loop to create a free-running DDS engine. Then in your main loop you could grab samples from that engine as needed via Registers or local variables. This is a non-trivial project, but there's no reason it can't be done.

The reason there is an interlock between interpolation and outputting both sine and cosine is that the VHDL takes advantage of the dual ports on a single hardware BRAM. You can either use the two ports to read adjacent points in parallel for interpolation, OR to read both a sine and cosine in parallel from the same memory. To do both at once would require another BRAM instance, so it's probably easiest to just use two separate instances of the Sine Wave Generator to accomplish that.

[Slev1n]

Hey guys,

JLewis is right the compilation fails. I am asking only these questions, as I want to specificate my signal performance. At the moment I use the function to get a sine and cosine for two 90° phase shifted phase selective detections with an acoustical signal. And as discussed here Square wave jitter I am facing problems generating square waves with exact frequencies in the upper 30kHz scale with the "Squre wave generator" function.

That is why I want to use the same sine, put it into a schmitt trigger (before this I will have to use a lowpass filter for the analog sine) and get a square wave for laser excitation with the same frequency.

As the sine output channel would have to be on the myRIO A-port it would have an amplitude between 0V and 5V.

[Source: http://pcbheaven.com/drcalculus/index.php?calc=st_nonsym_sp]

The square wave signal needs to have a duty cycle of 50%, the voltage levels should be 0V and 3,3V or higher as it goes onto a laserswitch.

Now a few questions:

1, Using 1kOhm for every resistor would give me a 50% duty cycle?

2, Would V+ have to be 5V?

3, Can you recommend me an Opamp for this operation?

kind regards

Slev1n