11-29-2009 11:59 AM
Dear Friends,
I have done an example for using the Spartan-3E kit StrataFlash Memory.
I got a problem I couldn't figure-out how to fix!
The problem is:
1- writing the following values to the StrataFlash:
1 2 3 4 5 6 7 8
2- Reading the written values from the same address, I get:
1 3 3 5 5 7 7 9
Also the reserved space on the FPGA is huge, I believe that this design can be optimized so that we can save some LUTs.
I wonder if someone can help and check my design, then advise the optimization points!
Also, I tried to read the identifier code, but I got the value 88h and I didn't understand this value!
P.S. Labview8.6.
Thanks,
12-09-2009 01:12 PM
12-10-2009 09:58 AM
I've never programmed he strataflash before on this board, but here are some resources I use for the Spartan:
http://pwo.fpga.be/coursematerial.html
LabVIEW FPGA Module Training for Xilinx Spartan 3E XUP Hardware
Not sure if the strataflash use is in there, however. Since these are academic only products, I dont think classes get that in depth on the boards.
12-10-2009 12:18 PM
Hello,
Thanks for your feedback but it seems theanswer has no relationship with the question, isn't? The below resources don't includeprogramming Strataflash!
The LABVIEW-FPGA Driver for Spartan-3E starterkit provides an example, but even this example is giving a wrong reading ormaybe writing in the first place! So, you may would ask the guy who wrote thedriver example about this problem. I don't think the problem is in the written example,it seems to me the problem has to be in the Strataflash settings/modes!
If you have done any example about programming Strataflashwith RIO or any other module, please do me a favor and attach.
Thanks & Looking forward to getting yourfeedback and test the attached example!